Insulating Adhesive Chip Carrier CTE Mismatch Stress
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Solution Overview
Problem
High thermo-mechanical stresses between silicon and copper materials due to differences in Coefficient of Thermal Expansion (CTE) cause fractures, bending, and warping in chip substrates, affecting the reliability and feasibility of subsequent manufacturing processes like laser drilling and wire bonding.
Innovation Solution
A chip arrangement featuring a chip carrier with insulating adhesive and chip contacts that accommodate the CTE differences, reducing thermo-mechanical stresses through electrical isolation and encapsulation, allowing for double-side cooling and redistribution structures to maintain chip integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If soldering or adhering a chip to a metal substrate at high temperature, then the chip is firmly attached to the substrate, but high thermo-mechanical stresses cause fractures, bending, and warping during cooling
Solution Approach 1:
The patent introduces an intermediary layer (insulating adhesive or underfill material) between the chip and metal substrate that acts as a stress buffer. This mediator has intermediate CTE properties between silicon and copper, reducing the thermo-mechanical stress differential while maintaining attachment strength during cooling cycles
Solution Approach 2:
The patent employs composite material structures including multi-layer substrates with different CTE properties and hybrid bonding approaches that combine mechanical attachment with stress distribution mechanisms, creating a composite system that accommodates thermal expansion differences without causing fractures
2Ease of manufacture
If using traditional soldering or adhering methods, then the chip is attached to the substrate, but subsequent manufacturing processes like laser drilling and wire bonding are affected by warping and bending
Solution Approach 1:
The patent applies preliminary stress compensation measures during the attachment process, such as pre-heating the substrate to match thermal expansion, applying adhesive in specific patterns that distribute stress evenly, or using fixtures that maintain flatness during cooling, thereby preventing warping before subsequent manufacturing steps
Solution Approach 2:
The patent modifies process parameters including attachment temperature profiles, cooling rates, and adhesive curing conditions to minimize thermal gradients and stress accumulation, maintaining substrate flatness within tolerances required for subsequent laser drilling and wire bonding operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces thermo-mechanical stresses, preventing fractures and warping, thereby enhancing the reliability and continuity of manufacturing processes by providing a stable interface between the chip and carrier.
Implementation Method 1
The CTE of silicon is 2.5×10−6/° C. while the CTE of copper is 16.5/° C. During cooling from a high temperature to a low temperature, different materials contract differently due to different CTEs.
Implementation Method 2
an insulating adhesive between the chip and the chip carrier to adhere the chip to the chip carrier
Data Source
AI summary
In various embodiments, a chip arrangement is provided. The chip arrangement may include a chip carrier and a chip mounted on the chip carrier. The chip may include at least two chip contacts and an insulating adhesive between the chip and the chip carrier to adhere the chip to the chip carrier. The at least two chip contacts may be electrically coupled to the chip carrier.