Insulating Transformer Chip Layout for High-Voltage Isolation
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Solution Overview
Problem
Current signal transmission devices face challenges in achieving high insulation withstand voltage while maintaining manufacturing simplicity and reducing warpage of semiconductor wafers, particularly in the design of transformer chips used in signal transmission systems.
Innovation Solution
The transformer chip is structured with a first unit and a second unit, each having a distinct element insulation layer, with low-voltage and high-voltage coils positioned to increase the distance between them without excessively increasing the thickness of the insulation layers, thereby enhancing insulation withstand voltage while minimizing warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the insulation layer is increased to achieve high insulation withstand voltage, then the insulation withstand voltage is improved, but the warpage of semiconductor wafers increases and manufacturing complexity increases
Solution Approach 1:
The insulation structure is divided into multiple separate insulation layers (first insulation layer and second insulation layer) positioned between different coil windings. This segmentation allows each layer to be optimized independently and reduces the warpage issue that would result from a single thick insulation layer, while collectively providing the required high insulation withstand voltage.
Solution Approach 2:
The patent positions insulation layers in multiple spatial dimensions - not only increasing thickness in the vertical direction but also strategically placing insulation layers at different horizontal positions between various coil windings. This multi-dimensional insulation approach achieves high withstand voltage without requiring excessive thickness in any single dimension, thereby minimizing wafer warpage.
2Reliability
If the thickness of the insulation layer is increased to achieve high insulation withstand voltage, then the insulation withstand voltage is improved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The insulation structure is divided into multiple separate insulation layers (first insulation layer and second insulation layer) positioned between different coil windings. This segmentation allows each layer to be optimized independently and reduces the warpage issue that would result from a single thick insulation layer, while collectively providing the required high insulation withstand voltage.
Solution Approach 2:
The patent positions insulation layers in multiple spatial dimensions - not only increasing thickness in the vertical direction but also strategically placing insulation layers at different horizontal positions between various coil windings. This multi-dimensional insulation approach achieves high withstand voltage without requiring excessive thickness in any single dimension, thereby minimizing wafer warpage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively increases the insulation withstand voltage of the transformer chip, simplifies the manufacturing process, and reduces warpage of semiconductor wafers, improving the overall performance and reliability of signal transmission devices.
Implementation Method 1
a first coil and a second coil are disposed in an element insulation layer and opposed to each other in a thickness-wise direction of the element insulation layer
Data Source
AI summary
An insulating chip includes: a first unit; and a second unit disposed on the first unit, wherein the first unit includes a first element insulation layer including a first element back surface and a first element head surface, a first insulation element embedded in the first element insulation layer, and a first connection electrode exposed from the first element back surface, the second unit includes a second element insulation layer including a second element back surface and a second element head surface, a second insulation element opposed to the first insulation element, and a second connection electrode exposed from the second element back surface, the first unit and the second unit are disposed so that the first element back surface is in contact with the second element back surface and the first connection electrode is electrically connected to the second connection electrode.