Insulating Columnar Layer Prevents Conductive Layer Sagging in 3D Memory
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Solution Overview
Problem
The challenge in manufacturing nonvolatile semiconductor memory devices lies in the difficulty of forming holes that penetrate conductive and insulating layers due to their differing etching rates, which can lead to defects and short circuits in the stepped portions of the peripheral region.
Innovation Solution
Incorporating an insulating columnar layer in the peripheral region to support the conductive layers and prevent sagging, thereby maintaining the structure and preventing short circuits during the formation of air gaps and ensuring the integrity of the memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If holes are formed to penetrate conductive layers and insulating layers, then memory holes can be created for memory cell formation, but the differing etching rates of conductive and insulating layers cause difficulty in forming holes in one lot and lead to defects
Solution Approach 1:
A sacrificial layer is introduced as an intermediary component between the conductive layers and the substrate. This sacrificial layer has etching characteristics that differ from both the conductive layers and the insulating layers, allowing it to be selectively removed to form holes that penetrate through the stacked structure. The sacrificial layer acts as a temporary mediator that enables hole formation without being damaged by the etching processes used for the conductive and insulating layers, thus resolving the contradiction between hole formation precision and manufacturing complexity.
2Adaptability or versatility
If stepped portions are formed in conductive layers for wiring contact, then connection to upper layer wiring is enabled, but faults may be generated in the stepped portion during manufacturing processes
Solution Approach 1:
The sacrificial layer is positioned and configured beforehand to provide structural support and protection to the stepped portions of the conductive layers during the manufacturing process. By maintaining the sacrificial layer in place before critical etching and processing steps, the stepped portions are cushioned against mechanical stress and potential faults that would otherwise occur during hole formation and material removal. This prior cushioning prevents defects in the stepped portions while preserving their wiring connection functionality.
3Productivity
If multiple layers with different etching rates are stacked, then three-dimensional memory structure is achieved, but it becomes difficult to form penetrating holes in one lot due to etching rate differences
Solution Approach 1:
The patent applies different material compositions and thicknesses to different regions of the stacked structure. The sacrificial layer is strategically positioned in specific regions where hole formation is required, with local variations in thickness and composition optimized for the etching process. This local quality approach allows the multi-layer structure to maintain its three-dimensional memory architecture while enabling consistent hole penetration through selective etching of the sacrificial layer in critical areas, thus resolving the contradiction between manufacturing efficiency and hole penetration consistency.
Data Source
AI summary
A nonvolatile semiconductor memory device includes a first region having a plurality of electrically rewritable memory cells disposed therein, and a second region adjacent to the first region. The nonvolatile semiconductor memory device includes a plurality of first conductive layers, a semiconductor layer, a charge storage layer, and an insulating columnar layer. The plurality of first conductive layers are stacked in the first region and the second region, and include a stepped portion in the second region, positions of ends of the plurality of first conductive layers being different in the stepped portion. The semiconductor layer is surrounded by the first conductive layers in the first region, includes a first columnar portion extending in a stacking direction. The charge storage layer is formed between the first conductive layers and a side surface of the first columnar portion. The insulating columnar layer is surrounded by the first conductive layers in the stepped portion, and includes a second columnar portion extending in the stacking direction and comprising an insulator.