Insulating Extension Patterns for Semiconductor Landing Pads
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Solution Overview
Problem
In highly integrated semiconductor devices, it is challenging to form conductive patterns that are electrically connected to contact patterns disposed between pattern structures without forming bridges and to reduce contact resistance, while also increasing the misalignment margin between pattern structures and conductive patterns.
Innovation Solution
The semiconductor device includes pattern structures with insulating spacers and extension patterns on opposing sidewalls, where the upper portions of the sidewalls are free of conductive landing pads to prevent bridge formation, and the extension patterns have a greater upper width than lower width to increase the contact area and reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive patterns are formed to connect contact patterns between pattern structures, then electrical connectivity is improved, but bridges between conductive patterns may form causing defects
Solution Approach 1:
The patent introduces extension patterns that protrude from the sidewalls of pattern structures in a lateral dimension, creating additional space for conductive patterns to connect contact patterns without requiring direct horizontal bridging between adjacent contacts. This vertical-protruding configuration separates the connection path from the bridge-risk zone.
Solution Approach 2:
The connection structure is divided into multiple segments: extension patterns protruding from sidewalls, conductive patterns filling spaces between extension patterns, and insulation patterns separating adjacent conductive patterns. This segmentation allows each component to perform its function independently while collectively solving the bridge formation problem.
2Reliability
If contact area is increased to reduce contact resistance, then electrical performance is improved, but device area increases reducing integration density
Solution Approach 1:
The extension patterns protrude laterally from the sidewalls of pattern structures, utilizing the vertical sidewall space to increase contact area without expanding the horizontal footprint. This allows contact pads to access larger contact surfaces while maintaining compact device dimensions.
Solution Approach 2:
The extension patterns are formed within the sidewall region of existing pattern structures, nesting the contact extension functionality within the vertical profile of the pattern structures rather than requiring additional horizontal space.
3Productivity
If design rule is decreased to increase integration, then device density is improved, but misalignment margin between patterns decreases
Solution Approach 1:
By utilizing the vertical sidewall dimension for extension patterns, the patent creates misalignment tolerance in the lateral direction without requiring increased horizontal spacing. The extension patterns can accommodate lateral shifts while maintaining electrical connection.
Solution Approach 2:
The extension patterns act as intermediary structures between the vertical pattern structures and the horizontal conductive patterns, providing a buffer zone that accommodates misalignment while ensuring electrical connection.
Data Source
AI summary
A semiconductor memory device includes a plurality of pattern structures respectively including a bit line and insulating spacers on sidewalls thereof protruding from a substrate. A plurality of insulating extension patterns are provided on opposing sidewalls of the pattern structures, and respectively extend from upper portions of the opposing sidewalls toward the substrate along the insulating spacers such that lower portions of the opposing sidewalls are free of the extension patterns. A plurality of buried contact patterns are provided on the substrate between the lower portions of the opposing sidewalls of adjacent pattern structures. Related fabrication methods are also discussed.