Insulating Fin Isolation for Nano-FET Source/Drain Leakage

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Solution Overview

Problem

As semiconductor devices continue to integrate more components into a given area through reduced minimum feature sizes, issues such as leakage between adjacent source/drain regions become significant, affecting the performance of nano-FETs.

Innovation Solution

The formation of insulating fins between source/drain regions, with different dielectric materials in dense and sparse regions, allows for better electrical isolation and separate etching processes, reducing pattern loading effects and enhancing device performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but leakage between adjacent source/drain regions increases

Engineering Contradiction:
Improveintegration densityVSAvoidleakage between source/drain regions
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent introduces insulating fins as separate isolation structures between adjacent source/drain regions. These fins divide the continuous substrate into isolated regions, preventing lateral epitaxial growth and reducing leakage current while maintaining high integration density through careful spacing and material selection.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different dielectric materials in different regions (dense regions vs. sparse regions) to optimize isolation performance locally. In dense regions, one dielectric material provides strong isolation, while in sparse regions, another material is used to minimize pattern loading effects during etching, thereby reducing leakage without compromising overall device performance.

Inventive Principle:
Principle #3Local quality

2Reliability

If insulating fins with different dielectric materials are used in dense and sparse regions, then electrical isolation is improved and pattern loading effects are reduced, but manufacturing process complexity increases

Engineering Contradiction:
Improveelectrical isolationVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent uses different dielectric materials specifically in dense regions versus sparse regions based on the local device architecture. This localized material selection optimizes electrical isolation where needed while simplifying the overall process by applying uniform materials where standard isolation is sufficient, thereby managing manufacturing complexity through targeted differentiation rather than universal complexity.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent forms the insulating fins with different dielectric materials during the epitaxial growth process or through preliminary deposition steps before final device fabrication. This preliminary structuring of isolation regions with appropriate materials establishes the foundation for subsequent processing steps, reducing the need for complex later modifications and managing manufacturing complexity through advance preparation.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250351480A1Transistor isolation regions and methods of forming the same
Publication Date: 2025.11.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250351480A1 patent drawing
  • US20250351480A1 patent drawing
  • US20250351480A1 patent drawing

AI summary

In an embodiment, a device includes: first source/drain regions; a first insulating fin between the first source/drain regions, the first insulating fin including a first lower insulating layer and a first upper insulating layer; second source/drain regions; and a second insulating fin between the second source/drain regions, the second insulating fin including a second lower insulating layer and a second upper insulating layer, the first lower insulating layer and the second lower insulating layer including the same dielectric material, the first upper insulating layer and the second upper insulating layer including different dielectric materials.