Insulating Gate Separation Structure for High Aspect Ratio ICs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As device dimensions shrink and packing densities increase, the aspect ratio of sacrificial gate structures in integrated circuits becomes higher, leading to incomplete cutting and residual conductive materials that can cause electrical shorts and decreased device performance or failure during the replacement gate structure formation process.
Innovation Solution
The formation of replacement gate structures involves creating a stepped insulating gate separation structure with a horizontally oriented bottom surface and a recessed surface, positioned at different levels above the substrate, to facilitate complete removal of sacrificial gate materials and prevent electrical shorts, using a two-step gate etching process and oxidizing anneal to convert residual conductive materials into insulating silicon dioxide.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are shrunk and packing densities are increased, then productivity and integration density are improved, but the aspect ratio of sacrificial gate structures becomes higher leading to incomplete cutting and residual conductive materials
Solution Approach 1:
The gate separation structure is divided into multiple level surfaces (first level substantially horizontal surface, second level recessed surface, third level horizontal surface) to segment the single cutting operation into multiple staged etching processes, allowing complete removal of sacrificial materials at different heights
Solution Approach 2:
The gate separation structure extends vertically with multiple levels and surfaces at different heights above the substrate, transforming a two-dimensional cutting problem into a three-dimensional multi-level structure that enables complete material removal through selective etching
2Productivity
If higher aspect ratio sacrificial gate structures are used to maintain packing density, then device integration is improved, but residual conductive materials cause electrical shorts and device failure
Solution Approach 1:
The multi-level gate separation structure is formed in advance with predetermined recessed surfaces and horizontal surfaces at different levels, preparing the etching pathways before sacrificial gate material deposition, ensuring complete material removal and electrical isolation are achieved
Solution Approach 2:
The gate separation structure acts as an intermediary between adjacent gate structures, with its multi-level surfaces providing physical and electrical isolation that prevents conductive material residue from causing shorts between neighboring devices
3Ease of manufacture
If conventional single-level gate separation structures are used, then manufacturing process is simpler, but incomplete removal of sacrificial materials occurs due to high aspect ratio
Solution Approach 1:
The gate separation structure is segmented into multiple etchable levels with distinct horizontal surfaces, allowing the manufacturing process to be divided into staged etching operations that systematically remove sacrificial materials from different heights
Solution Approach 2:
The formation process uses periodic alternating deposition and etching cycles to build and refine the multi-level gate separation structure, with each cycle adding a level or surface that contributes to the final complete material removal capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures the complete removal of sacrificial gate materials, reduces the risk of electrical shorts, and enhances the formation of quality replacement gate structures, improving device performance and reliability.
Implementation Method 1
oxidizing anneal to convert residual conductive materials into insulating silicon dioxide
Data Source
AI summary
One illustrative IC product disclosed herein includes first and second final gate structures and an insulating gate separation structure positioned between the first and second final gate structures. In one embodiment, the insulating gate separation structure has a stepped bottom surface with a substantially horizontally oriented bottom central surface that is surrounded by a substantially horizontally oriented recessed surface, wherein the substantially horizontally oriented bottom central surface is positioned a first level above the substrate and the substantially horizontally oriented recessed surface is positioned at a second level above the substrate, wherein the second level is greater than the first level.