Insulating Guide Film Layout for Stable IC Wiring Isolation

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Solution Overview

Problem

As IC devices continue to downscale, there is a need for stable insulation distances between wirings and contacts while reducing their area occupation, and ensuring reliable operation and accuracy.

Innovation Solution

The integration of a fin-type active region with a multilayered conductive film structure and a unified conductive pattern, along with an insulating guide film, to maintain insulation distances and prevent short circuits, while using materials with different compositions for the conductive patterns.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the area of IC devices is reduced through downscaling, then device density and integration are improved, but insulation distances between wirings and contacts become unstable and reliability deteriorates

Engineering Contradiction:
Improvedevice areaVSAvoidinsulation distance stability
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The gate line is divided into a multilayered conductive film structure with multiple conductive patterns (first conductive pattern, second conductive pattern, etc.) made of different materials. This segmentation allows each layer to contribute to different functions, with the uppermost insulating surface providing enhanced insulation while the lower layers provide conductivity, thus maintaining reliable insulation distances in downscaled devices

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from planar conductive structures to three-dimensional multilayered structures. By stacking multiple conductive patterns vertically and providing an insulating uppermost surface, the design utilizes the vertical dimension to simultaneously achieve compact area occupation and stable insulation distances, resolving the contradiction between downscaling and reliability

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If multiple conductive materials are used in the gate line structure, then electrical performance and conductivity are improved, but manufacturing complexity increases

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidconductive film structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Multiple conductive patterns made of different materials are merged into a single integrated gate line structure. The first conductive pattern, second conductive pattern, and other conductive patterns are stacked and interconnected to form a unified multilayered conductive film structure, achieving improved electrical performance while managing manufacturing complexity through integration

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If insulating structures are added to maintain insulation distances, then reliability is improved, but area occupation increases

Engineering Contradiction:
Improveinsulation reliabilityVSAvoidarea occupation
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

Instead of expanding insulating structures horizontally which would increase area occupation, the patent utilizes the vertical dimension by creating a multilayered conductive film structure with an insulating uppermost surface. This vertical arrangement provides effective insulation between adjacent conductive patterns while maintaining compact area occupation, as the insulation is achieved through layering rather than lateral expansion

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12364007B2Integrated circuit device including insulating guide film between adjacent conductive patterns
Publication Date: 2025.07.15 SAMSUNG ELECTRONICS CO LTD
  • US12364007B2 patent drawing
  • US12364007B2 patent drawing
  • US12364007B2 patent drawing

AI summary

An integrated circuit (IC) device including a fin-type active region on a substrate and a gate line on the fin-type active and having a first uppermost surface at a first vertical level, an insulating spacer covering a sidewall of the gate line and having a second uppermost surface at the first vertical level, and an insulating guide film covering the second uppermost surface of the insulating spacer may be provided. The gate line may include a multilayered conductive film structure that includes a plurality of conductive patterns and have a top surface defined by the conductive patterns, which includes at least first and second conductive patterns including different materials from each other and a unified conductive pattern that is in contact with a top surface of each of the conductive patterns and has a top surface that defines the first uppermost surface.