Insulating Layer Patterning With AS-ALD Selective Blocking

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Solution Overview

Problem

Conventional top-down optical lithography for semiconductor devices is costly and time-consuming, particularly for ultrafine patterns below 10 nm, with issues like non-uniformity in pattern line width, alignment, and surface roughness, and new patterning technologies are needed to improve precision and reduce costs.

Innovation Solution

A method using Area-Selective Atomic Layer Deposition (AS-ALD) to form a selective blocking layer and insulating layer on substrates with different dielectric layers, enabling precise pattern formation without additional masks, using precursors like those in chemical formulas 1 and 2, and repeating the process for enhanced selectivity and aspect ratio.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional top-down optical lithography is used for ultrafine pattern formation, then pattern formation capability is achieved, but manufacturing cost and processing time increase significantly

Engineering Contradiction:
Improvepattern formation precisionVSAvoidprocessing time
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent inverts the conventional top-down approach by using bottom-up self-assembly of block copolymers to form patterns. Instead of imposing patterns from above through lithography, the system allows patterns to emerge spontaneously from molecular self-organization, fundamentally reversing the patterning paradigm and achieving ultrafine features without expensive lithography equipment

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The block copolymer system performs self-service by automatically self-assembling into ordered nanostructures through spontaneous phase separation. The polymers autonomously organize into domains with specific spacing and morphology without requiring external patterning tools, masks, or complex alignment processes, thereby eliminating the need for expensive lithography equipment and reducing processing time

Inventive Principle:
Principle #25Self-service

2Manufacturing precision

If conventional top-down optical lithography is used for ultrafine pattern formation, then pattern formation capability is achieved, but manufacturing cost increases significantly

Engineering Contradiction:
Improvepattern formation precisionVSAvoidmanufacturing cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent employs inexpensive block copolymer materials that can be processed in standard laboratory equipment rather than requiring millions of dollars in lithography tooling. The self-assembling polymers act as disposable sacrificial templates that define patterns during formation and are subsequently removed, replacing expensive reusable lithography equipment with cheap consumable materials

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The block copolymer system performs self-service by automatically self-assembling into ordered nanostructures through spontaneous phase separation. The polymers autonomously organize into domains with specific spacing and morphology without requiring external patterning tools, masks, or complex alignment processes, thereby eliminating the need for expensive lithography equipment and reducing processing time

Inventive Principle:
Principle #25Self-service

3Manufacturing precision

If dip-coating method is used for selective layer formation, then selective blocking is achieved, but processing time increases to several hours

Engineering Contradiction:
ImproveselectivityVSAvoidprocessing time
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent replaces the mechanical dip-coating process with a chemical vapor deposition approach where precursors are delivered via vapor phase. This substitution eliminates the slow liquid infiltration mechanism of dip-coating and enables rapid conformal film formation through vapor-phase chemical reactions, reducing processing time from hours to minutes while maintaining selective blocking capability

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent employs periodic pulsed delivery of precursor gases in sequence, where each precursor is introduced for a brief period followed by a purge step. This periodic action enables complete reaction cycles to occur rapidly in the vapor phase, achieving selective layer formation in minutes compared to the continuous slow infiltration required by dip-coating methods

Inventive Principle:
Principle #19Periodic action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Achieves highly uniform and high-density insulating layer patterns with excellent selectivity and reduced processing time, forming precise patterns in minutes rather than hours, and improving selectivity and aspect ratio without external exposure.

Implementation Method 1

effectively utilizing the surface reaction characteristics of ALD processes to selectively form precise atomic-level thin layers

Methodology Applied
Scientific EffectSurface reaction: Adsorption

Implementation Method 2

Area-Selective Atomic Layer Deposition (AS-ALD, also known as ASD)

Methodology Applied
Scientific EffectAtomic layer deposition: Physical Vapour Deposition

Implementation Method 3

etching a portion of an upper portion of the insulating layer

Methodology Applied
Scientific EffectEtching: Ablation

Data Source

PatentUS20260052917A1Method for forming an insulating layer pattern and semiconductor device
Publication Date: 2026.02.19 DONGJIN SEMICHEM CO LTD
  • US20260052917A1 patent drawing
  • US20260052917A1 patent drawing
  • US20260052917A1 patent drawing

AI summary

A method for forming an insulating layer pattern includes providing a substrate including two or more different types of dielectric layer regions; selectively forming a blocking layer on the substrate to include a first region on which a blocking layer is formed and a second region on which no blocking layer is formed or the blocking layer is formed less than in the first region; selectively forming an insulating layer on the second region; and etching a portion of an upper portion of the insulating layer.