Insulating Layer for BBUL Package Via Alignment
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Solution Overview
Problem
Existing microelectronic packaging technologies face challenges in forming vias to copper bumps, leading to misalignment, yield loss, and non-uniformities due to thick Build-Up Films (ABF), which result in larger via diameters, smaller gaps, and reduced trace routing capabilities, increasing costs and complexity.
Innovation Solution
The use of an insulating layer to encompass die sidewalls, converting vias to conductive through vias for improved alignment and routing, allowing for smaller, more accurately aligned traces and increased space for routing, thereby reducing the number of build-up layers and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If thick Build-Up Films (ABF) are used, then structural support is improved, but via alignment precision deteriorates and manufacturing complexity increases
Solution Approach 1:
The patent divides the thick ABF structure into multiple thinner ABF layers separated by intermediate insulating layers. This segmentation maintains the overall structural support while reducing the via diameter and improving alignment precision for each individual via formation step.
Solution Approach 2:
The patent introduces an additional vertical dimension by adding intermediate insulating layers between ABF layers. This creates a multi-layer stack structure that allows better control over via alignment and routing in the horizontal plane while maintaining structural support through the vertical stacking.
2Strength
If thick Build-Up Films (ABF) are used, then structural support is improved, but routing flexibility deteriorates
Solution Approach 1:
By segmenting the thick ABF into multiple thinner layers with intermediate insulating layers, the patent creates more routing planes and pathways. This segmentation increases routing flexibility by allowing traces to be routed in multiple layers while maintaining overall structural support.
Solution Approach 2:
The multi-layer stack structure with intermediate insulating layers adds vertical dimensionality, enabling three-dimensional routing paths. This increases routing flexibility by allowing traces to switch between layers and providing more routing options without compromising structural support.
3Ease of manufacture
If via diameter is increased, then manufacturing ease is improved, but space for trace routing deteriorates
Solution Approach 1:
The patent segments the via formation process into multiple steps across different layers, allowing smaller via diameters to be used while maintaining ease of manufacture through standardized processing for each layer. The intermediate insulating layers provide separation that facilitates precise via formation.
Solution Approach 2:
By moving to a multi-layer structure, the patent compensates for smaller via diameters by providing additional vertical space for routing. The intermediate insulating layers create new routing planes that increase the available space for traces without requiring larger via diameters.
4Device complexity
If number of build-up layers is reduced, then manufacturing cost is reduced, but I/O density deteriorates
Solution Approach 1:
The patent uses the vertical dimension by stacking multiple thin ABF layers with intermediate insulating layers to achieve high I/O density in a compact vertical profile. This allows increased I/O density without proportionally increasing the number of build-up layers, as the intermediate layers enable more efficient space utilization.
Solution Approach 2:
The patent changes the parameters of the ABF layers by using thinner individual layers with intermediate insulating layers, rather than fewer thick layers. This parameter change allows for higher I/O density while controlling the overall layer count and maintaining manufacturing feasibility.
Data Source
AI summary
An apparatus including a die including a dielectric material on a device side, an insulating layer surrounding a die area and embedding a thickness dimension of the die; and a carrier including a plurality of layers of conductive material disposed on the device side of the die, a first one of the layers of conductive materials being formed on the insulating layer and patterned into traces at least a portion of which are connected to respective contact points on the die. A method including disposing a die on a sacrificial substrate with a device side of the die opposite the sacrificial substrate; disposing a mold on the sacrificial substrate around; introducing an insulating material into a chase of the mold; removing the mold; forming a carrier on the insulating material adjacent a device side of a die; and separating the die and the carrier from the sacrificial substrate.