Insulating Layer Flatness in Semiconductor Packages

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Solution Overview

Problem

Semiconductor packages face challenges in achieving flatness of insulating layers, which can lead to short-circuits and hinder the redistribution of connection terminals, particularly in fan-out wafer level packages where complex functionality and miniaturization are required.

Innovation Solution

The implementation of a double coating process for insulating layers on wiring patterns protruding from a support member to enhance flatness, using the same material for both coatings, which alleviates thickness deviations and prevents short-circuits by forming a planarized surface.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a single insulating coating is formed on protruding wiring patterns, then the manufacturing process is simple, but the flatness of the insulating layer is poor leading to short-circuit risks

Engineering Contradiction:
Improveflatness of insulating layerVSAvoidcoating process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The insulating layer is divided into multiple coatings (first insulating coating and second insulating coating) formed in sequence. The first coating provides base insulation while the second coating enhances flatness, thereby resolving the contradiction between manufacturing simplicity and flatness quality by segmenting the coating process into functional stages.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first insulating coating is formed preliminarily on the protruding wiring patterns before the second coating is applied. This preliminary action creates a foundation that reduces the thickness deviation for the subsequent second coating, improving overall flatness while maintaining a systematic manufacturing approach.

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If wiring patterns protrude from the support member, then connection terminals can be redistributed outwardly, but thickness deviation of the insulating layer increases causing short-circuits

Engineering Contradiction:
Improveredistribution of connection terminalsVSAvoidflatness of insulating layer
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The solution addresses the thickness deviation problem by adding a vertical dimension through multiple coating layers. The second insulating coating compensates for the height variation caused by protruding wiring patterns, transforming a two-dimensional flatness problem into a three-dimensional layered structure that achieves effective flatness.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The invention changes the parameter of coating thickness by applying a second insulating coating with specific thickness control. This parameter change compensates for the thickness deviation caused by protruding wiring patterns, ensuring adequate insulation distance and preventing short-circuits while maintaining the ability to redistribute connection terminals outwardly.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If the insulating layer thickness is increased to prevent short-circuits, then reliability improves, but the flatness deteriorates due to thickness deviation

Engineering Contradiction:
Improveshort-circuit preventionVSAvoidflatness of insulating layer
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The second insulating coating is applied selectively to regions with greater thickness deviation caused by protruding wiring patterns. This local quality approach ensures that additional thickness is provided only where needed for short-circuit prevention, while maintaining better overall flatness compared to uniformly increasing the entire insulating layer thickness.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10622273B2Semiconductor package with improved flatness of an insulating layer formed on patterns
Publication Date: 2020.04.14 SAMSUNG ELECTRONICS CO LTD
  • US10622273B2 patent drawing
  • US10622273B2 patent drawing
  • US10622273B2 patent drawing

AI summary

A semiconductor package includes a support member having first and second surfaces, having a cavity, and including a wiring structure, a semiconductor chip having connection pads, a connection member including a first insulating layer, a first redistribution layer on the first insulating layer, and a plurality of first vias connecting the wiring structure and the connection pads to the first redistribution layer and an encapsulant encapsulating the semiconductor chip, The wiring structure includes wiring patterns disposed on the second surface of the support member, and the first insulating layer includes a first insulating coating covering the wiring patterns and a second insulating coating disposed on the first insulating coating and having a higher level of flatness than that of the first insulating coating.