Insulating Layer as Mask and Polishing Stopper in Semiconductor Super Junction
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Solution Overview
Problem
Conventional semiconductor device manufacturing methods require separate processes for forming an oxide layer as a mask and a polishing stopper, which can lead to defects and variations in the super junction structure.
Innovation Solution
A method where a single electrically insulating layer is used as both a mask for forming trenches and a polishing stopper during the planarization process, with the layer being selectively removed and reused to ensure uniformity and prevent defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a first oxide layer is formed as a polishing stopper and a second oxide layer is formed as a mask separately, then the polishing stopper function and mask function are both achieved, but the manufacturing process becomes complex and time-consuming
Solution Approach 1:
The patent combines the polishing stopper layer and mask layer into a single integrated insulating layer structure. The insulating layer is formed once and then selectively removed in different regions to serve both as a polishing stopper (in chip regions) and as a mask for trench formation (on scribe lines), eliminating the need for separate formation processes for two distinct oxide layers.
Solution Approach 2:
The insulating layer is designed to perform multiple functions: it serves as a polishing stopper during CMP processing to control surface planarity, and simultaneously acts as a mask layer during wet etching to define trench patterns on scribe lines. This multi-functional design reduces the total number of process steps while maintaining both functions effectively.
2Ease of manufacture
If the oxide layer is left near the trench opening to serve as mask, then the mask function is achieved, but it becomes difficult to fill the trench with epitaxial layer and defects occur
Solution Approach 1:
The patent applies different treatments to different regions of the insulating layer. In chip regions, the insulating layer is completely removed to enable proper trench filling and high-quality epitaxial growth. On scribe lines, the insulating layer is retained to serve as a mask for trench definition. This spatial differentiation of the insulating layer's presence ensures both good trench filling and proper mask functionality.
3Reliability
If separate processes are used for forming polishing stopper and mask, then both functions are achieved, but manufacturing time and productivity are reduced
Solution Approach 1:
The patent merges the formation of the polishing stopper and mask into a single insulating layer formation process. By forming one insulating layer that serves both purposes, the number of deposition processes is reduced from two separate oxide layer formations to one, directly improving manufacturing efficiency and productivity.
Solution Approach 2:
The insulating layer is selectively removed (discarded) in chip regions after serving its dual purpose, while being retained (recovered) on scribe lines where it continues to function as a mask. This selective removal strategy optimizes the process by eliminating unnecessary material in regions where it is no longer needed while preserving it where it provides continued value.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach eliminates the need for additional manufacturing processes, reduces defects, and achieves consistent breakdown voltage across semiconductor chips by using the insulating layer as both a mask and a polishing stopper, thereby enhancing the manufacturing efficiency and quality of semiconductor devices with a super junction structure.
Implementation Method 1
wet etching is performed by using hydrofluoric acid so that the second oxide layer can be removed without removing the first oxide layer
Implementation Method 2
a p-type epitaxial layer is epitaxially grown over the main surface side of the semiconductor substrate so that the trenches can be filled with the epitaxial layer
Implementation Method 3
the epitaxial layer on the main surface side of the semiconductor substrate is polished and planarized by chemical mechanical polishing (CME) or the like
Data Source
AI summary
In a semiconductor device manufacturing method, an insulating layer is formed on a front surface of a semiconductor substrate. Trenches are formed in the substrate by using the insulating layer as a mask so that a first portion of the insulating layer is located on the front surface between the trenches and that a second portion of the insulating layer is located on the front surface at a position other than between the trenches. The entire first portion is removed, and the second portion around an opening of each trench is removed. The trenches are filled with an epitaxial layer by epitaxially growing the epitaxial layer over the front surface side. The front surface side is polished by using the remaining second portion as a polishing stopper.