Insulating Layer for Semiconductor Saw Street Stability
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Solution Overview
Problem
Semiconductor devices face challenges with unstable contact resistance and plasma stability during oxide etching in Fan-Out Wafer Level Chip Scale Packages (FO-WLCSP), particularly due to out-gassing from the molding area affecting plasma stability in Physical Vapor Deposition (PVD) processes.
Innovation Solution
A method involving the deposition of an encapsulant between semiconductor die, designating a portion as a saw street, and forming an insulating layer over the saw street to stabilize contact resistance and plasma during oxide etching, which includes forming an insulating layer over the saw street and substrate edge to minimize out-gassing and ensure reliable singulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an insulating layer is formed over the saw street and substrate edge, then contact resistance stability and plasma stability during oxide etching are improved, but out-gassing from the molding area affects plasma stability
Solution Approach 1:
The insulating layer acts as an intermediary barrier between the molding area and the PVD process environment. By covering the saw street and substrate edge, it prevents out-gassing from the molding area from directly affecting the plasma stability during oxide etching, while maintaining stable contact resistance for edge pads formed in PVD
2Reliability
If an insulating layer is formed over the saw street and substrate edge, then plasma stability during oxide etching is improved, but the complexity of the manufacturing process increases
Solution Approach 1:
The insulating layer is formed in advance before the oxide etching process and PVD steps. This preliminary action ensures that the molding area is sealed off beforehand, preventing out-gassing from affecting subsequent plasma processes, thereby maintaining plasma stability without requiring additional process steps during etching
3Reliability
If the edge pads are formed in PVD, then electrical connectivity is achieved, but contact resistance becomes unstable due to out-gassing from molding area
Solution Approach 1:
The insulating layer serves as a protective intermediary that covers the molding area before PVD and oxide etching processes. This barrier prevents out-gassing from the molding area from disrupting plasma stability, ensuring stable contact resistance for edge pads formed during PVD
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The insulating layer enhances contact resistance stability and plasma stability during oxide etching, reducing particle contamination and improving the reliability of semiconductor device singulation by minimizing out-gassing from the molding area, thus ensuring consistent and efficient manufacturing processes.
Implementation Method 1
plasma stability during oxide etching
Implementation Method 2
minimize out-gassing from the molding area
Data Source
AI summary
A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die.