Insulating Structure Under Metal Line for 3D Package Reliability
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Solution Overview
Problem
Current semiconductor devices face challenges in improving electrical characteristics and reliability, particularly in 3D package structures where via plug structures and metal interconnections are involved, due to limitations in insulating layers and their positional relationships with metal layers.
Innovation Solution
A semiconductor device structure is developed with a via plug passing through a substrate, featuring a metal layer at its end, and an insulating structure with a layered structure that varies according to its positional relationship with the metal layer, enhancing electrical characteristics and reliability by forming a different depth on the side surface adjacent to the metal layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional insulating layer structure is used under the metal interconnection layer, then the manufacturing process is simple, but the electrical characteristics and reliability are insufficient
Solution Approach 1:
The insulating layer is divided into multiple distinct layers (first insulating layer and second insulating layer) with different material compositions and functions. The first insulating layer provides mechanical support and stress relief, while the second insulating layer provides electrical insulation and planarization, allowing each layer to optimize its specific function rather than requiring a single complex layer
Solution Approach 2:
Different regions of the insulating structure have different properties - the first insulating layer has different material composition and thickness characteristics compared to the second insulating layer. This allows local optimization where each layer is tailored to its specific functional requirements under different portions of the metal interconnection layer
2Reliability
If the insulating layer has uniform structure, then the manufacturing is easier, but signal transmission delays and parasitic capacitance cannot be optimized
Solution Approach 1:
The insulating structure is segmented into multiple layers with different thicknesses and material properties, enabling independent optimization of electrical characteristics for each layer while maintaining manufacturing feasibility through standardized deposition processes for each layer type
Solution Approach 2:
The patent changes physical parameters of the insulating layers including thickness, material composition, and dielectric constant to optimize electrical performance. By adjusting these parameters across different layers, signal transmission delays and parasitic capacitance are reduced while maintaining manufacturing precision through controlled parameter variations
Data Source
AI summary
A semiconductor device including a via plug formed on a substrate and a metal layer for interconnection formed at an end of the via plug, wherein an insulating structure is under the metal layer for interconnection and the insulating structure has a different layered structure according to a positional relationship with the metal layer for interconnection is disclosed.