Semiconductor Insulation Etching to Prevent Sidewall Cavities
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Solution Overview
Problem
The formation of voids on sidewalls during the etching process of insulation layers in semiconductor manufacturing, particularly in CMOS and LDMOS processes, due to the isotropy of wet etching, which affects the integrity and performance of semiconductor devices.
Innovation Solution
A method combining dry etching and wet etching processes to control the thickness of the insulation layer, where dry etching removes a significant portion initially, followed by isotropic wet etching to expose the substrate surface, minimizing cavity formation and maintaining surface topography, using techniques like ion milling or plasma etching and wet etching solutions such as hydrofluoric acid.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wet etching is used to remove insulation layer, then etching speed is improved, but cavity formation on sidewalls occurs due to isotropy
Solution Approach 1:
The etching process is divided into two distinct stages: first a dry etching process removes a first portion of the insulation layer, followed by a wet etching process that removes a remaining portion. This segmentation allows each process to be optimized for its specific function - dry etching provides directional control to prevent cavities, while wet etching provides high removal speed for the remaining material.
Solution Approach 2:
The invention changes the etching parameters by switching between two different etching chemistries and modes - from plasma-based dry etching to chemical-based wet etching. This parameter change enables the process to achieve both high precision in the first stage and high productivity in the second stage, resolving the contradiction between etching speed and sidewall integrity.
2Productivity
If isotropic wet etching is used to expose substrate surface, then etching efficiency is improved, but surface topography changes and voids form
Solution Approach 1:
The dry etching process is performed as a preliminary action before the wet etching step. This preliminary action removes the majority of the insulation layer thickness in a controlled, anisotropic manner that preserves sidewall geometry and prevents cavity formation. By performing this preparatory step, the subsequent isotropic wet etching can efficiently remove the remaining thin portion without causing significant topography changes or void formation.
3Manufacturing precision
If dry etching is used to remove insulation layer, then sidewall integrity is maintained, but etching speed decreases
Solution Approach 1:
The dry etching process is used to remove a first portion (partial action) of the insulation layer, specifically designed to remove the majority of the thickness while maintaining sidewall integrity. The remaining portion is then removed by wet etching. This partial application of dry etching optimizes the balance between precision and productivity by using the high-speed wet etching for the final removal step where precision is less critical.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the formation of cavities on sidewalls and substrates, enhancing the structural integrity and performance of semiconductor devices by maintaining a flat surface topography and preventing voids at the junctions, thereby improving the reliability of metal salicide formation.
Implementation Method 1
performing a dry etching process to etch a first portion of the insulation layer
Implementation Method 2
using techniques like ion milling or plasma etching
Implementation Method 3
performing a wet etching process to etch a remaining portion of insulation layer
Implementation Method 4
using wet etching solutions such as hydrofluoric acid
Data Source
AI summary
A method of etching for a semiconductor structure having a substrate, and a first structure located on part of a top surface of the substrate, where two side surfaces of the first structure are configured as sidewalls, can include: forming an insulation layer to cover the substrate, the first structure, and the sidewalls; performing a dry etching process to etch a first portion of the insulation layer; and performing a wet etching process to etch a remaining portion of the insulation layer, in order to expose the top surface of the substrate, where a thickness of the first portion of the insulation layer etched by the dry etching process is greater than a thickness of the remaining portion of insulation layer etched by the wet etching process, in order to decrease formation of cavity in the substrate and/or sidewalls.