Consecutive Integer Frequency Divider With 50% Duty-Cycle Correction
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Solution Overview
Problem
Current phase-locked loop circuits are limited in achieving 50%-duty-cycle consecutive integer frequency division, restricting their application due to the inability to handle higher duty cycle requirements, especially with divisors beyond 2^n-1, where n is a binary bit.
Innovation Solution
A frequency divider circuit comprising a non-50%-duty-cycle consecutive integer frequency divider, a D flip-flop module, and a logic OR gate is used to receive and process clock signals, achieving a 50%-duty-cycle output by delaying and combining clock signals, allowing frequency division with any divisor, including odd and even numbers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If O dividers are used to achieve 50%-duty-cycle frequency division, then the duty cycle is improved to 50%, but the frequency division is limited to divisors 1, 2, 4, 8, ..., 2^n-1
Solution Approach 1:
The frequency division function is segmented into two independent parts: a conventional divider that handles the division ratio and a duty cycle correction module that ensures 50% duty cycle. This segmentation allows the divider to support any integer divisor while the correction module maintains precise 50% duty cycle output, resolving the contradiction between duty cycle precision and frequency division range.
Solution Approach 2:
A duty cycle correction module is introduced as an intermediary component between the conventional divider and the output. This mediator receives the divided signal and actively adjusts its duty cycle to 50%, enabling the system to achieve both arbitrary frequency division ratios and precise 50% duty cycle without limiting the divisor options.
2Productivity
If M dividers and N dividers are used for consecutive frequency division, then frequency division is achieved, but the duty cycle is a quotient of 1 and a frequency divisor instead of 50%
Solution Approach 1:
A duty cycle correction module is introduced as an intermediary component between the conventional divider and the output. This mediator receives the divided signal and actively adjusts its duty cycle to 50%, enabling the system to achieve both arbitrary frequency division ratios and precise 50% duty cycle without limiting the divisor options.
Solution Approach 2:
The duty cycle parameter is actively changed from its natural value (1/divisor) to the desired value (50%) through the duty cycle correction module. This parameter transformation allows the system to maintain high productivity in frequency division while achieving precise duty cycle control, resolving the contradiction between these two requirements.
3Adaptability or versatility
If conventional frequency dividers are used, then frequency division with any divisor is possible, but the duty cycle cannot be maintained at 50%
Solution Approach 1:
The frequency division function is segmented into two independent parts: a conventional divider that handles the division ratio and a duty cycle correction module that ensures 50% duty cycle. This segmentation allows the divider to support any integer divisor while the correction module maintains precise 50% duty cycle output, resolving the contradiction between duty cycle precision and frequency division range.
Solution Approach 2:
The duty cycle parameter is actively changed from its natural value (1/divisor) to the desired value (50%) through the duty cycle correction module. This parameter transformation allows the system to maintain high productivity in frequency division while achieving precise duty cycle control, resolving the contradiction between these two requirements.
Data Source
AI summary
Embodiments described herein relate to a 50%-duty-cycle consecutive integer frequency divider and a phase-locked loop circuit having the frequency divider. The frequency divider includes a consecutive integer frequency divider module having a non-50%-duty-cycle, wherein the module receives a clock signal CLK and an input control signal CB and outputs a consecutive frequency division clock signal CLK1 comprising a non-50% duty cycle; a D flip-flop module for receiving the clock signal CLK and the consecutive frequency division clock signal CLK1 and outputting at least one clock signal CLKx; and a logic OR gate module for receiving the consecutive frequency division clock signal CLK1 and the at least one clock signal CLKx, and outputting an output clock signal CLKout comprising a 50% duty cycle.