Formal Verification of Integer Divider Hardware Designs
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Solution Overview
Problem
Integrated circuit hardware designs for integer division have been difficult to verify using formal verification methods, especially for designs with large input bit widths, as they require an unmanageable number of simulation test signals and often result in inconclusive or error-prone results.
Innovation Solution
The proposed method involves verifying a base property and one or more range reduction properties using a formal verification tool to exhaustively verify the operation of an integer divider for non-negative inputs, and optionally sign relation properties for negative inputs, leveraging implementation similarity to reduce the number of test cases and increase verification efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If formal verification is used to verify integrated circuit hardware designs for integer division, then verification completeness is improved, but verification complexity increases due to unmanageable number of test cases
Solution Approach 1:
The verification process is segmented into two distinct phases: (1) verifying a base property for a subset of input pairs, and (2) verifying range reduction properties that relate different input ranges. This segmentation divides the unmanageable complete verification into manageable pieces that can be handled separately and then combined through logical reasoning.
Solution Approach 2:
Instead of verifying all possible input pairs exhaustively, the method verifies a subset of input pairs (base property) and then uses range reduction properties to extend the verification coverage. This partial action approach verifies enough cases to establish patterns that generalize to the entire input space without requiring complete exhaustive verification.
2Measurement precision
If exhaustive simulation-based verification is performed, then verification accuracy is improved, but verification time becomes unmanageably long
Solution Approach 1:
The base property verification is performed as a preliminary action on a subset of input pairs. This preliminary verification establishes foundational correctness that can then be extended to the complete input space through range reduction properties, avoiding the need to perform exhaustive verification from scratch.
Solution Approach 2:
Range reduction properties act as intermediaries that connect the base property verification to the complete input space verification. These properties serve as logical bridges that allow results from a subset of cases to be extended to all cases without requiring direct verification of each individual case.
3Reliability
If the number of test vectors is increased to cover all input pairs, then verification coverage is improved, but resource requirements become unmanageable
Solution Approach 1:
The base property and range reduction properties serve universal functions that apply across the entire input space. By verifying these general properties once, the method achieves verification coverage for all input pairs without needing to create specific test vectors for each individual case, making the verification process scalable to large input widths.
Data Source
AI summary
Computer-implemented methods of verifying an integrated circuit hardware design to implement an integer divider wherein the integer divider is configured to receive a numerator N and a denominator D and output a quotient q and a remainder r. The method includes (a) verifying a base property is true for the integrated circuit hardware design and (b) formally verifying that one or more range reduction properties are true for the integrated circuit hardware design. The base property is configured to verify that an instantiation of the integrated circuit hardware design will generate a correct output pair q,r in response to any input pair N,D in a subset of non-negative input pairs. The one or more range reduction properties are configured to verify that if an instantiation of the integrated circuit hardware design will generate an output pair q,r in response to a non-negative input pair N,D then an instantiation of the integrated circuit hardware design to implement the integer divider will generate an output pair q′,r′ that has a predetermined relationship with q and r in response to another non-negative input pair N′,D where N and N′ have one of one or more predetermined relationships.