Integer Division Circuit Using Bit-Shifting Normalization

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Solution Overview

Problem

Modern microprocessors rely on software algorithms for advanced mathematical calculations like multiplication and division, which are slow, particularly for high-volume division operations in applications such as flash lidar, necessitating a hardware-based solution for faster integer division.

Innovation Solution

An integer division circuit comprising bit-shifting circuits to normalize dividend and divisor, a divider tree circuit for division, and additional logic for sign determination and quotient adjustment, enabling hardware-accelerated integer division within a processor.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If software algorithms are used for division operations, then the microprocessor can perform basic addition and subtraction using the ALU, but the division operations become slow, particularly for high-volume division operations

Engineering Contradiction:

Improvedivision operation speedVSAvoidhardware circuit complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent replaces the software-based division algorithm with a dedicated hardware division circuit. This substitution eliminates the sequential execution overhead of software loops and enables parallel hardware computation, achieving significant speedup for division operations while maintaining acceptable circuit complexity through modular design

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The division circuit is segmented into multiple functional blocks including a normalization unit with bit-shifting circuits, a main division unit with divider tree, and a result adjustment unit. This segmentation allows each block to perform a specific function efficiently and enables pipelining of operations across different segments, improving overall throughput

Inventive Principle:

Principle #1Segmentation

2Speed

If a hardware division circuit is implemented, then division operations become faster, but the circuit complexity increases due to additional normalization and adjustment logic

Engineering Contradiction:

Improvedivision operation speedVSAvoidcircuit structure complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The normalization unit performs preliminary bit-shifting operations on the dividend and divisor before they enter the main division unit. By pre-normalizing the inputs to a standard format, the main divider tree operates on consistent data structures, simplifying its logic and reducing the complexity of the overall circuit while maintaining high speed

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Instead of adjusting the division algorithm to handle variable-length inputs directly, the patent inverts the approach by normalizing inputs to a fixed format first, then performing the division. This inversion simplifies the main division logic at the cost of adding normalization steps, but the overall circuit complexity is reduced through this systematic approach

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS10599396B2Integer division circuit and method of performing integer division in hardware

Publication Date: 2020.03.24 CONTINENTAL AUTONOMOUS MOBILITY US LLC

AI summary

An integer division circuit includes a first bit-shifting circuit configured to shift the bits of a dividend to produce a normalized dividend. The circuit also includes a second bit-shifting circuit configured to shift the bits of a divisor to produce a normalized divisor. A divider tree circuit is configured to divide the normalized dividend by the normalized divisor to produce a normalized quotient. The circuit further includes a third bit-shifting circuit configured to shift the bits of the normalized quotient to produce a quotient.