Integer Division Frequency Synthesizer for Data Rate Conversion
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Solution Overview
Problem
Conventional devices with two network layers operating at different data rates require fractional clock dividers, leading to increased circuit costs and complexity.
Innovation Solution
A data transmission system using a frequency synthesizer with an integer division factor to generate a divided clock for the upper network layer, reducing circuit costs and avoiding data overflow/underflow by adjusting the operation frequency and clock enable/disable cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fractional clock divider is employed to obtain a divided clock for different data rates, then the data rate conversion between network layers is achieved, but circuit costs and design difficulty increase significantly
Solution Approach 1:
The patent changes the division factor from fractional to integer values, simplifying the clock divider design. By using integer division factors (N1, N2, N3) instead of fractional division, the circuit complexity is reduced while still achieving the required data rate conversion between network layers through multiple clock domains.
Solution Approach 2:
The patent segments the clock division process into multiple stages with different integer division factors. Instead of using a single complex fractional divider, the system uses multiple integer dividers (dividing by N1, N2, N3) to achieve the overall frequency conversion, making each stage simpler and more manageable.
2Device complexity
If a frequency synthesizer with integer division factor is used, then circuit costs are reduced, but the flexibility in achieving exact frequency ratios may be limited
Solution Approach 1:
The overall frequency conversion is segmented into multiple integer division stages. By dividing the frequency conversion into multiple steps with different integer factors (N1, N2, N3), the system achieves complex frequency ratios using only simple integer dividers, maintaining flexibility while reducing circuit complexity.
Solution Approach 2:
The integer division frequency synthesizer is designed to be universal by accepting different integer division factors. The same basic circuit structure can achieve multiple frequency ratios by simply changing the division factors, providing adaptability without requiring different hardware for each frequency conversion scenario.
3Reliability
If the operation frequency of the first processing circuit is adjusted, then data overflow and underflow are avoided, but the clock synchronization complexity increases
Solution Approach 1:
The system uses feedback mechanisms to monitor the data buffer status and adjust the operation frequency of the first processing circuit accordingly. By detecting potential overflow or underflow conditions and dynamically adjusting the clock frequency, the system maintains reliable data transmission while managing synchronization through controlled frequency adaptation.
Data Source
AI summary
A data transmission apparatus disposed within two network layers operative at different data rates is provided. The data transmission apparatus is coupled to a clock generator which provides a reference clock for a lower network layer and is coupled to a frequency synthesizer with an integer division factor that generates a divided clock for an upper network layer according to the reference clock and the integer division factor. The data transmission apparatus includes a first processing circuit and a second processing circuit. The first processing circuit corresponding to the upper network layer receives and transmits data by using the divided clock as its operation frequency. The second processing circuit corresponding to the lower network layer receives and transmits data from the first processing circuit by using the reference clock as an operation frequency for encoding data. The divided clock is generated from the frequency synthesizer with the integer division factor.