Integer Arithmetic Encoding Conversion for FPU-Limited Embedded Systems
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Solution Overview
Problem
Embedded systems lacking a floating-point unit (FPU) are unable to perform floating-point operations, limiting their capability to handle IEEE 754 encoding formats, which are commonly used for binary floating-point numbers.
Innovation Solution
A method and system for encoding format conversion using integer arithmetic operations, enabling conversion between linear encoding formats like Linear11 and IEEE 754 formats, allowing embedded systems to perform floating-point operations without an FPU.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If floating-point operations are performed using IEEE 754 encoding format, then computational precision and capability are improved, but device complexity and resource consumption increase due to requiring a floating-point unit
Solution Approach 1:
The patent replaces the floating-point unit (hardware mechanism) with integer arithmetic operations (software algorithm). By converting floating-point numbers to a custom encoding format that uses only integer operations, the system achieves floating-point computational capability without requiring dedicated floating-point hardware, thus reducing device complexity while maintaining precision
Solution Approach 2:
The patent changes the encoding parameter representation by defining a new format where the floating-point number is represented as an encoded value combining mantissa and exponent components. This parameter transformation allows integer arithmetic to simulate floating-point behavior, resolving the contradiction between precision and device complexity
2Adaptability or versatility
If a floating-point unit is added to enable IEEE 754 operations, then adaptability to floating-point formats is improved, but manufacturing cost and device complexity increase
Solution Approach 1:
The patent makes the integer arithmetic unit universal by designing an encoding/decoding mechanism that can handle both integer and floating-point operations through the same hardware. The encoded floating-point format is processed using standard integer arithmetic instructions, allowing a single processor to perform multiple function types without requiring separate floating-point hardware, thereby improving ease of manufacture while maintaining format adaptability
Solution Approach 2:
The patent introduces an intermediary encoding format that acts as a bridge between integer hardware and floating-point requirements. This intermediate representation allows the system to communicate floating-point concepts through integer operations, achieving format compatibility without direct floating-point hardware support
3Device complexity
If floating-point operations are implemented without an FPU, then device complexity is reduced, but computational accuracy and reliability deteriorate
Solution Approach 1:
The patent segments the floating-point number into distinct components (encoded value, exponent, mantissa) that can be manipulated separately using integer operations. By breaking down the floating-point representation into manageable integer components, the system maintains computational reliability through precise control of each segment while avoiding the need for complex floating-point hardware
Data Source
AI summary
A method for performing encoding format conversion with integer arithmetic operations and a system performing the method are provided. The system includes a target device that adopts a power-management bus (PMBus), and operates an embedded system that is only capable of integer arithmetic operation without any floating-point unit. In the method, a floating-point arithmetic encoding format value is inputted. After a logarithm value of the floating-point value is obtained by extracting an exponent value from a binary representation of the floating-point value, a new exponent value can be obtained through a control flow. A new mantissa value is then calculated according to the floating-point value, the exponent value and the new exponent value. A new value that is a linear encoding format value converted from the floating-point arithmetic encoding format value is generated by combining the new exponent value and the new mantissa value.