Integer Image Scaling Processor Eliminates Dividers
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Solution Overview
Problem
Conventional image scaling processors require a divider and a floating point unit, leading to complex device configurations and redundant operations due to the need for scaling up and storing image data, as well as introducing checkerboard distortions during arbitrary scaling processes.
Innovation Solution
An image scaling processor that calculates interpolation coefficients to perform arbitrary scaling without using a divider or floating point unit, utilizing a coefficient computing circuit, multiplier, adder, selector, and shift circuit to convert input image data to U/D times, where U and D are natural numbers, by iteratively adding multiplied data and adjusting bit counts, while avoiding decimal portions and using integer operations to eliminate redundancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional image scaling process is used, then image scaling can be performed, but device complexity increases due to requirement of divider and floating point unit
Solution Approach 1:
The patent transforms floating point interpolation coefficients into integer representations by scaling them to have denominator 2^m. This parameter transformation allows the system to perform arbitrary image scaling using only integer arithmetic operations (addition, multiplication, shifting), thereby eliminating the need for floating point units and dividers in the hardware architecture.
Solution Approach 2:
The patent replaces the mechanical/computational requirements for floating point division and multiplication with simpler integer-based operations. By pre-calculating and storing integer interpolation coefficients that sum to 2^m, the system substitutes complex floating point computations with straightforward integer addition and bit shifting operations, significantly simplifying the hardware device configuration.
2Adaptability or versatility
If scaling up and storing intermediate image data is performed, then arbitrary scaling can be achieved, but redundant operation and memory are required
Solution Approach 1:
The patent performs preliminary action by pre-calculating and storing integer interpolation coefficients for various scaling factors before the actual image processing. These pre-computed coefficients are stored in a lookup table, allowing the system to directly compute scaled image data without first creating an intermediate upscaled image, thereby eliminating redundant memory operations.
Solution Approach 2:
The patent extracts the essential interpolation computation from the conventional two-step process (upscale then downscale). By using pre-computed integer interpolation coefficients that directly compute the final scaled values, the system extracts and performs only the necessary interpolation operation, eliminating the redundant intermediate scaling step and associated memory requirements.
3Adaptability or versatility
If conventional interpolation technique is used, then image scaling is achieved, but checkerboard distortions occur
Solution Approach 1:
The patent changes the parameter representation of interpolation coefficients from floating point to integer format where coefficients sum to 2^m. This parameter change enables the use of integer arithmetic that naturally preserves precision and eliminates the checkerboard distortions caused by floating point rounding errors and division operations in conventional methods.
Data Source
AI summary
An image scaling processor includes: a coefficient computing circuit that calculates interpolation coefficients to be used in an image scaling process; a multiplier that multiplies input image data by the interpolation coefficients provided from the coefficient computing circuit such that the interpolation coefficients respectively correspond to input pixels constituting the input image data; an adder that iteratively adds pieces of multiplied data output from the multiplier and obtains a total sum of the pieces of multiplied data for a predetermined number of the input pixels; a selector that outputs a total sum of the multiplied data at a timing at which the total sum of the pieces of multiplied data is obtained for the predetermined number of the input pixels; and a shift circuit that shifts an output of the selector to adjust a bit count of the output image data to a bit count of the input image data.


