Integer-N Frequency Synthesizer for Arbitrary Frequency Output
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Solution Overview
Problem
Conventional oscillators are limited in their ability to generate arbitrary frequencies, leading to system malfunctions when standard frequencies are not met, as they often rely on fractional-N phase lock loops that increase phase noise and spurious emissions.
Innovation Solution
The use of frequency synthesizers with integer dividers, which allow for the selection of divider settings to achieve desired output frequencies without fractional dividing, enabling operation with arbitrary frequencies by considering various grid spacings and fine-tuning techniques to reduce frequency errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fractional-N phase lock loops are used to generate arbitrary frequencies, then frequency flexibility is improved, but phase noise and spurious emissions increase significantly
Solution Approach 1:
The patent segments the frequency synthesis process into two independent parts: an integer-N PLL that generates a clean base frequency, and a separate frequency offset mechanism that adds arbitrary frequency shifts. This segmentation allows the main PLL to operate with integer dividers only, avoiding the phase noise problems of fractional-N PLLs while still achieving arbitrary frequency output through the offset addition.
Solution Approach 2:
The patent introduces an intermediary frequency offset signal that mediates between the clean integer-N PLL output and the desired arbitrary frequency. This offset signal acts as a bridge, allowing the system to achieve frequency flexibility without compromising the clean spectral characteristics of the main PLL, thus resolving the contradiction between adaptability and harmful emissions.
2Object-generated harmful factors
If integer dividers are used in phase lock loops, then phase noise and spurious emissions are reduced, but frequency selection flexibility is limited to standard frequencies
Solution Approach 1:
The patent merges two frequency generation approaches: the clean integer-N PLL output and the arbitrary frequency offset. By combining these two sources through frequency addition, the system achieves both low phase noise (from the integer-N PLL) and arbitrary frequency selection (from the offset mechanism), thus resolving the contradiction between harmful factor reduction and flexibility improvement.
Solution Approach 2:
The patent changes the frequency parameter by introducing a variable offset that can be adjusted independently of the main PLL. This allows the output frequency to be tuned to arbitrary values while the main PLL continues to operate with fixed integer dividers, maintaining low phase noise while achieving frequency flexibility through parameter modification.
3Object-generated harmful factors
If higher comparison frequencies are used in phase lock loops, then phase noise is reduced, but the system becomes more sensitive to frequency mismatches with standard oscillators
Solution Approach 1:
The patent introduces dynamic frequency offset adjustment that adapts to the actual oscillator frequency. The system dynamically calculates and applies the appropriate offset to compensate for frequency mismatches, allowing the use of higher comparison frequencies for low phase noise while maintaining reliability through real-time adaptation to the oscillator's actual frequency characteristics.
Data Source
AI summary
Frequency synthesizers for use with oscillators that generate an arbitrary frequency are described, as well as related devices and methods. Divider information can be generated or otherwise accessed for use in configuring a phase lock loop device that is adapted for coupling with the oscillator, where the phase lock loop device can include a plurality of integer dividers without utilizing a fractional divider, where the divider information can include frequency deviations corresponding to groups of integer divider settings for the phase lock loop device, and where each deviation of the frequency deviations can be based on a frequency differential between a standard operating frequency and an output frequency for the phase lock loop utilizing one group of integer divider settings from the groups of integer divider settings.