Multi-Phase Integer-N PLL Clock Generator for Spur Reduction
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Solution Overview
Problem
Conventional integer-N PLL-based clock generators produce spurious content in high-frequency output clock signals due to phase frequency detectors and charge pumps, which are large and high-voltage, causing power supply transients and parasitic coupling, leading to unwanted spurious content on the output clock signal, especially when using high-frequency reference clocks.
Innovation Solution
The solution involves an integer-N phase-locked loop clock generator with multiple phase frequency detectors and charge pumps, where each phase frequency detector and charge pump pair operates independently to reduce spurious content by generating a plurality of phases and dividing the output clock signal, thereby distributing the detection and correction process across multiple cycles, reducing the amplitude and frequency of spurious content and avoiding the need for high-frequency reference clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional integer-N PLL-based clock generator uses a single phase frequency detector and charge pump, then the circuit can operate at high frequency, but spurious content is generated in the output clock signal due to power supply transients and parasitic coupling
Solution Approach 1:
The patent divides the single phase frequency detector and charge pump into multiple parallel instances (first phase frequency detector, second phase frequency detector, first charge pump, second charge pump). Each detector-pump pair operates independently on different phases of the clock signal, segmenting the harmful spurious generation events across multiple cycles rather than concentrating them in a single cycle, thereby reducing peak spurious content amplitude
Solution Approach 2:
The patent employs periodic phase shifting where the multiple phase frequency detectors and charge pumps operate on different phases of the clock signal in a periodic manner. This distributes the detection and correction events across multiple clock cycles, spreading out the spurious content generation in time and reducing its disruptive effect on the output signal
2Object-generated harmful factors
If high-frequency reference clocks are used to push spurious content out of band, then spurious content is distance from output clock signal, but cost and complexity increase
Solution Approach 1:
The patent changes the temporal distribution parameter of the phase detection and charge pumping operations by introducing multiple phases with different timing. Instead of changing the reference clock frequency parameter, the system maintains the same frequency but alters the phase distribution parameter, spreading events across multiple cycles to push spurious content out of band through time-domain distribution rather than frequency-domain separation
3Reliability
If large, high voltage phase frequency detectors and charge pumps are used, then the VCO can be controlled at high voltage for high quality output, but power supply transients are caused and disturbances are introduced during each phase detection event
Solution Approach 1:
The patent segments the large, high-voltage phase frequency detector and charge pump into multiple smaller parallel instances. Each instance handles a portion of the control current requirement, distributing the total power demand across multiple cycles. This maintains the necessary high-voltage control capability for VCO operation while reducing peak power supply transients by dividing the load among multiple detector-pump pairs operating at different phases
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces spurious content in the output clock signal by distributing the detection and correction process across multiple cycles, resulting in smaller, uniform spikes of spurious content that occur at the same frequency as the output clock, making it less disruptive to wireless transceiver components and reducing the need for high-frequency reference clocks, thus lowering costs and complexity.
Implementation Method 1
a plurality of phase frequency detectors for comparing a plurality of phase pairs and generating a pulse signal, each pair comprising one of the plurality of phases of the first phase generator and one of the plurality of phases of the second phase generator
Implementation Method 2
a plurality of charge pumps for controlling the voltage controlled oscillator based on the pulse signal
Implementation Method 3
a voltage controlled oscillator, having a control input, for generating an output clock signal, the frequency of the output clock signal being proportional to a control voltage on the control input of the voltage controlled oscillator
Implementation Method 4
a clock divider for dividing down a signal from the voltage controlled oscillator by N to generate a divided down signal
Data Source
AI summary
An integer-N phase-locked loop based clock generator for generating an output clock signal with a frequency N multiples of a reference clock signal, and a method for same, wherein N is a positive integer. The integer-N clock phase-locked loop based generator comprises a reference clock, a voltage controlled oscillator, a clock divider, a first and second phase generator for generating a plurality of phases of the reference clock signal and divided down output clock signal, a plurality of phase frequency detectors and charge pumps. The method comprises generating a reference clock and an output clock signals, generating a plurality of phases of a divided down output clock signal and reference clock signal, comparing the plurality of phases, and changing the frequency of the output clock signal based on the comparison.