Integer-N Clock Clean-Up PLL for Fractional-N Spur Suppression
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Solution Overview
Problem
Wireless communication devices face performance degradation due to undesired spurs in clock signals, particularly from fractional-N frequency synthesizers, which introduce abrupt frequency jumps and spreading spurs that couple as noise, degrading receiver sensitivity and in-band performance.
Innovation Solution
Implementing an integer-N phase-locked loop (PLL) as a clock clean-up PLL within the RFIC to receive and process clock signals with fractional-N frequency synthesizers, attenuating abrupt frequency jumps and suppressing spreading spurs by using an integer divider ratio, resulting in a cleaner clock signal with reduced spurs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fractional-N frequency synthesizer is used to generate the clock signal, then frequency flexibility and adaptability are improved, but spurs and noise are introduced that degrade receiver performance
Solution Approach 1:
An integer-N clean-up PLL is introduced as an intermediary between the fractional-N frequency synthesizer and the ADC. This mediator circuit receives the clock signal with spurs from the fractional-N synthesizer, processes it through integer-N division and loop filtering, and outputs a clean clock signal with reduced spurs to the ADC, thus resolving the contradiction between frequency flexibility and spur generation
Solution Approach 2:
The clock signal generation system is segmented into two independent stages: a fractional-N frequency synthesizer stage for frequency flexibility and an integer-N clean-up PLL stage for spur reduction. This segmentation allows each stage to optimize for its specific function without compromising the other, enabling both frequency adaptability and low spur performance
2Area of stationary object
If the ADC is placed close to the LNA on the same integrated circuit substrate, then device integration and compactness are improved, but noise coupling from the ADC to the LNA increases
Solution Approach 1:
The clean-up PLL acts as an intermediary signal conditioning circuit between the clock source and the ADC, providing a clean clock signal that reduces electromagnetic noise generation. This allows the ADC to operate with lower noise emissions, enabling closer placement to the LNA on the same substrate while maintaining performance
Solution Approach 2:
The invention converts the potentially harmful effect of close proximity (noise coupling) into a benefit by using the clean-up PLL to eliminate the noise source. The tight integration that would normally cause noise coupling is instead leveraged to reduce overall device area, while the clean-up PLL ensures noise-free operation
Data Source
AI summary
A clock clean-up phase-locked loop (PLL) that may reduce spurs and improve performance of a receiver is described. In one exemplary design, an integrated circuit includes a PLL and an analog-to-digital converter (ADC). The PLL receives a first clock signal generated with a fractional divider ratio and having spurs due to abrupt frequency jumps. The first clock signal may be generated by a fractional-N frequency synthesizer external to the integrated circuit. The PLL generates a second clock signal with an integer divider ratio and having reduced spurs. The ADC digitizes an analog baseband signal based on the second clock signal and provides digital samples. The integrated circuit may further include a low noise amplifier (LNA), which may observe less spurs coupled via the substrate of the integrated circuit due to the use of the PLL to clean up the first clock signal.