Integral Adhesive Structure for Semiconductor Chip Stacking
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Solution Overview
Problem
Existing semiconductor package technologies face challenges in enhancing mechanical endurance and efficiently bonding stacked semiconductor chips, particularly in high-density chip stacks where adhesive structures fail to provide adequate mechanical support and electrical insulation.
Innovation Solution
A semiconductor package design featuring an integral adhesive structure with a continuously convex sidewall that fills spaces between the package substrate and stacked semiconductor chips, including an extension protruding from the outer sidewalls of the chips, formed by thermally compressing non-conductive films to create a robust and uniform bonding layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional adhesive structures are used between stacked semiconductor chips, then the bonding process can be performed, but the mechanical endurance is insufficient
Solution Approach 1:
The adhesive structure extends not only vertically between chips but also horizontally with extensions that protrude from outer sidewalls of the semiconductor chips, creating a three-dimensional adhesive network that provides enhanced mechanical support and distributes stress across multiple dimensions
Solution Approach 2:
The adhesive structure is formed by thermally compressing non-conductive films, creating a composite material that combines adhesive properties with electrical insulation, providing both mechanical bonding strength and electrical isolation between stacked chips
2Reliability
If adhesive structures are applied to bond stacked chips, then electrical connectivity can be achieved, but electrical insulation is inadequate
Solution Approach 1:
The non-conductive adhesive structure serves as an intermediary material between stacked semiconductor chips, providing electrical insulation while maintaining mechanical bonding, thus preventing electrical interference between adjacent chips in the stack
Solution Approach 2:
The adhesive structure combines bonding functionality with electrical insulation properties through the use of thermally compressed non-conductive films, creating a composite material that simultaneously addresses both mechanical and electrical requirements
3Ease of manufacture
If multiple adhesive structures are used for each chip stack, then bonding can be performed, but manufacturing complexity increases
Solution Approach 1:
The adhesive structure is designed as an integral, continuous formation that spans multiple chip interfaces, merging what would traditionally require separate adhesive applications into a single unified structure, thereby simplifying the manufacturing process
Solution Approach 2:
The single adhesive structure performs multiple functions: bonding chips together, providing electrical insulation, and extending to cover sidewalls for additional mechanical support, eliminating the need for multiple specialized adhesive components
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly improves mechanical endurance and electrical connectivity by providing a strong, uniform adhesive layer that insulates connection terminals and enhances the bonding process efficiency, allowing for the stacking of multiple chips with improved reliability and reduced manufacturing complexity.
Implementation Method 1
formed by thermally compressing non-conductive films to create a robust and uniform bonding layer
Data Source
AI summary
A semiconductor package includes a first semiconductor chip stacked on a package substrate in which a first surface of the first semiconductor chip faces the package substrate and a second surface that is opposite to the first surface, a second semiconductor chip stacked on the first semiconductor chip that includes a third surface facing the first semiconductor chip and a fourth surface that is opposite to the third surface, and an integral adhesive structure that substantially continuously fills a first space between the package substrate and the first semiconductor chip and a second space between the first and second semiconductor chips. The integral adhesive structure includes an extension protruding from outer sidewalls of the first and second semiconductor chips. The extension has one continuously convex sidewall between a level of the first surface and a level of the fourth surface.