Integral IC Display Apparatus Bezel Width Reduction
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Solution Overview
Problem
Display apparatuses face challenges in reducing bezel width due to the separate manufacturing and bonding of gate and data drivers, which increases manufacturing costs and design constraints, and result in increased power consumption.
Innovation Solution
An integral integrated circuit is used, incorporating a gate channel and data channel, with a level shifter on the display panel or flexible circuit substrate to generate gate signals, reducing bezel width and power consumption by decoding methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gate driver and data driver are independently manufactured and bonded, then manufacturing flexibility is maintained, but bezel width increases and manufacturing cost increases
Solution Approach 1:
The patent combines the gate driver and data driver into a single integrated circuit chip that is directly mounted on the display panel. This merging eliminates the need for separate manufacturing and bonding processes, thereby reducing the bezel width while maintaining manufacturing flexibility through integrated circuit design.
2Ease of manufacture
If gate driver and data driver are independently manufactured and bonded, then manufacturing flexibility is maintained, but manufacturing cost increases
Solution Approach 1:
By merging the gate driver and data driver into a single integrated circuit, the patent reduces the number of manufacturing steps and components required, thereby lowering manufacturing cost while preserving design flexibility through integrated circuit architecture.
3Length of stationary object
If integral integrated circuit is used, then bezel width is reduced, but design constraints are created
Solution Approach 1:
The patent employs dynamic routing and configurable signal paths in the integrated circuit, allowing the same IC to adapt to different display panel layouts and requirements. This dynamic adaptability enables bezel reduction without sacrificing design flexibility.
4Use of energy by moving object
If decoding method is used to generate gate signal, then power consumption is reduced, but signal processing complexity increases
Solution Approach 1:
The patent implements periodic scanning and sequential activation of pixel rows through decoding methods, where gate signals are generated in time-division multiplexed sequences. This periodic action reduces overall power consumption by activating circuits only when needed, while the complexity is managed through systematic sequential processing.
Data Source
AI summary
A display apparatus includes an integral integrated circuit and a display panel. The integral integrated circuit includes a gate channel which outputs a gate primitive signal and a data channel which outputs a data voltage. The display panel includes a level shifter which amplifies the gate primitive signal to generate a gate signal. The display panel is configured to display an image based on the gate signal and the data voltage. The display panel includes a first gate line extending in a first direction and a second gate line extending in a second direction. The second direction is different from the first direction. The second gate line is connected to the first gate line. The level shifter is connected to the second gate line.