Integral Terminal Circuit Assembly via Electroless Plating
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Solution Overview
Problem
Traditional printed circuit boards (PCBs) face challenges in achieving high density and miniaturization due to limitations in via structure creation, such as taper, carbon contamination, and reliability issues, especially with dry film technology, which increases costs and complexity.
Innovation Solution
The integration of a bulk conductive material with electro-less and electro-plated core terminals, allowing for the creation of fine line high density circuits with undercuts and precise placement of conductive structures, enabling low resistance connections and increased density without the need for laser ablation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If laser ablation is used to create via structures for fine line high density circuits, then via creation is enabled, but significant taper, carbon contamination, layer-to-layer shorting during plating, and high resistance interconnections occur
Solution Approach 1:
The patent removes the laser ablation step from the via creation process entirely, extracting the harmful effects (taper, carbon contamination, shorting) by eliminating the source. Instead, mechanical drilling or punching methods are used to create via holes, followed by electroless and electro-plating to form conductive paths without the detrimental byproducts of laser processing.
Solution Approach 2:
The patent employs sacrificial materials or temporary structures during manufacturing that are removed after serving their purpose. For example, mandrels or support structures may be used during plating to ensure uniform deposit and then removed, allowing for reliable via formation without the need for expensive and problematic laser equipment.
2Ease of manufacture
If traditional dry film technology is used for via creation, then via structures can be formed, but costs increase and manufacturing complexity increases
Solution Approach 1:
The patent replaces the chemical-based dry film photolithography process with a more direct mechanical approach. Instead of applying, exposing, and developing dry film layers to define via locations, the invention uses mechanical drilling, punching, or laser-free ablation methods to create via holes directly, followed by simple plating processes. This substitution reduces the number of manufacturing steps and eliminates the complexity of dry film handling and processing.
3Productivity
If feature sizes and line spacing are reduced to achieve miniaturization, then circuit density increases, but via structure creation becomes more difficult with traditional methods
Solution Approach 1:
The patent changes the fundamental parameters of via creation by moving from chemical etching through dry film to mechanical or controlled physical removal methods. This allows for precise control of via dimensions even at reduced feature sizes and line spacing. The electroless and electro-plating processes also provide precise control over conductor fill, enabling reliable via formation at high density without the registration and taper problems of traditional methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of high density circuit structures with fine contact-to-contact spacing, reducing manufacturing costs and improving reliability, while allowing for the creation of blind or buried vias on tight pitches without the limitations of traditional methods.
Implementation Method 1
an array of integral terminals plated on a first circuit member including an electro-lessly plated shell
Implementation Method 2
an electro-plated core
Data Source
AI summary
A method of making an array of integral terminals on a circuit assembly. The method includes the steps of depositing at least a first liquid dielectric layer on the first surface of a first circuit member, imaged to include a plurality of first recesses corresponding to the array of integral terminals. The selected surfaces of the first recesses are processed to accept electro-less conductive plating deposition. Electro-lessly plating is applied to the selected surfaces of the first recesses to create a plurality of first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. Electro-plating is applied to the electro-less plating to substantially first recesses with a conductive material. The steps of depositing, processing, electro-less plating, and electro-plating are repeated to form the integral terminals of a desired shape. The dielectric layers are removed to expose the terminals.