Integrated 3D Memory Devices for Computing-in-Memory Applications
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Solution Overview
Problem
Existing 3D memory devices have limitations in integrating multiple memory structures on separate chips, leading to increased propagation delay and signal drop during data transfer, which affects performance and storage density in computing-in-memory applications.
Innovation Solution
Integrating multiple memory structures, such as AND and NAND memory configurations, on a single chip, where one structure is optimized for high-speed computing and the other for dense data storage, eliminating the need for separate chip integration and associated delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory structures are integrated on separate chips, then storage density is improved, but propagation delay and signal drop increase
Solution Approach 1:
The patent combines multiple memory structures (AND memory and NAND memory) onto a single chip substrate, eliminating the need for separate chips and inter-chip connections. This merging approach maintains high storage density while reducing propagation delay and signal drop by enabling direct on-chip data transfer between memory structures.
Solution Approach 2:
The patent employs three-dimensional vertical stacking of memory structures within the single chip, transitioning from two-dimensional lateral integration to three-dimensional vertical integration. This dimensional change allows multiple memory types to coexist on one chip without increasing lateral footprint, thereby maintaining storage density while enabling direct fast access between structures.
2Quantity of substance
If multiple memory structures are integrated on separate chips, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple memory structures onto a single chip with unified control logic and data pathways, reducing the complexity associated with managing multiple separate chips, inter-chip connections, and external routing. The integrated design simplifies the overall system architecture while maintaining high storage capacity.
3Quantity of substance
If minimum feature size is reduced, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions to three-dimensional vertical stacking, which increases integration density by utilizing the vertical dimension rather than continuously reducing lateral feature sizes. This approach mitigates the need for ever-smaller feature sizes and their associated manufacturing precision challenges, as density improvement is achieved through vertical layering rather than lateral miniaturization.
Data Source
AI summary
A semiconductor device includes a memory array that includes a plurality of memory strings each extending in a vertical direction and having a plurality of memory cells. Each of the plurality of memory cells has a drain terminal and a source terminal, and the drain terminal of a first one of the plurality of memory cells and the source terminal of a second one of the plurality of memory cells are electrically coupled to a first conductor structure and a second conductor structure respectively extending in a lateral direction. Each of the plurality of memory strings further includes a vertical memory layer, and a semiconductor channel having a vertical portion coupled to the memory layer and a lateral portion coupled to a top surface of the first conductor structure. The top surface of the first conductor structure is not in contact with the memory layer.