Integrated Alignment Overlay Mark for Semiconductor Lithography
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Solution Overview
Problem
In semiconductor manufacturing, the separate formation of alignment and overlay marks on different shot regions leads to inefficient wafer area usage, increased material costs, and imprecise alignment accuracy due to potential errors between the marks.
Innovation Solution
An integrated alignment and overlay mark system where both marks are formed in the same shot region, with the overlay mark inside the alignment mark, allowing for precise error calculation and reduced scribe lane area, enabling efficient die manufacturing and improved alignment accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If alignment mark and overlay mark are formed in different shot regions, then each mark can be individually formed and measured, but the scribe lane occupies excessive wafer area and reduces manufacturing efficiency
Solution Approach 1:
The patent combines the alignment mark and overlay mark into a single integrated mark structure located in the same shot region. The alignment mark and overlay mark share the same physical space on the wafer, eliminating the need for separate scribe lane allocations. This merging approach maintains the individual measurement capabilities while significantly reducing the total area occupied, thereby improving wafer area utilization and manufacturing efficiency.
2Ease of manufacture
If alignment mark and overlay mark are formed in different shot regions, then the marks can be independently formed, but the measurement results cannot precisely represent the alignment accuracy due to exposure errors
Solution Approach 1:
By forming both the alignment mark and overlay mark within the same shot region, the patent ensures they undergo identical exposure conditions. This eliminates exposure-related errors that would otherwise exist when marks are formed in different regions. The integrated structure allows both marks to be formed simultaneously in one exposure shot, ensuring measurement precision while maintaining manufacturing simplicity.
3Adaptability or versatility
If two individual marks are formed on the scribe lane, then alignment and overlay functions are provided, but the large scribe lane increases material cost and reduces manufacturing benefit
Solution Approach 1:
The patent merges the alignment mark and overlay mark into a single integrated structure that performs both functions simultaneously. This eliminates the need for a large scribe lane that would be required to accommodate two separate marks, thereby reducing wafer material consumption and cost. The integrated mark maintains both alignment and overlay measurement capabilities while minimizing the occupied area.
Solution Approach 2:
The integrated mark structure serves multiple functions - it acts as both an alignment mark and an overlay mark within the same physical structure. This multi-functionality allows the system to perform both alignment and overlay measurements using a single mark configuration, eliminating the need for separate marks and reducing the associated material requirements and costs.
Data Source
AI summary
An integrated alignment and overlay mark for detecting the exposed errors of the photolithography process between a pre-layer and a current layer is disclosed. The integrated alignment and overlay mark includes an alignment mark and an overlay mark in the same shot region. The alignment mark is formed surrounding the overlay mark; therefore, the gap or the orientation between the pre-layer and the current layer can be calculated in order to check the alignment accuracy of photolithography process.