Integrated Alignment and Overlay Mark for Semiconductor Wafer Registration
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Solution Overview
Problem
Current semiconductor wafer manufacturing processes face challenges in alignment and overlay accuracy due to measurement deviations between different tools and inefficient use of chip area, as alignment and overlay marks are measured separately and occupy valuable space.
Innovation Solution
An integrated alignment and overlay mark is introduced, combining a pre-layer pattern for reticle-to-wafer registration with a current-layer pattern in the exposure tool, allowing for simultaneous measurement and reducing chip area usage by incorporating the alignment mark into the overlay mark.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If alignment mark and overlay mark are measured separately by different tools, then each tool can perform its specific measurement function, but measurement deviations accumulate and total accuracy deteriorates
Solution Approach 1:
The patent combines the alignment mark and overlay mark into a single integrated mark structure that can be measured by a single tool. The integrated mark includes both pre-layer pattern and current-layer pattern components that serve dual purposes: alignment reference and overlay reference, eliminating the need for separate measurement tools and reducing cumulative measurement deviations.
Solution Approach 2:
The integrated alignment and overlay mark serves multiple functions simultaneously. It acts as both an alignment reference for reticle-to-wafer registration and an overlay reference for measuring registration accuracy between patterned layers, allowing a single measurement system to perform both functions and improve overall measurement reliability.
2Manufacturing precision
If alignment mark and overlay mark are located in different regions of wafer, then each mark can be optimized for its specific function, but valuable chip area is wasted
Solution Approach 1:
The patent merges the alignment mark and overlay mark into a single integrated structure located at the same position on the wafer. This integration eliminates the need for separate regions for each mark type, thereby conserving valuable chip area while maintaining both alignment and overlay measurement capabilities within a compact footprint.
3Ease of manufacture
If separate alignment mark and overlay mark regions are used, then each mark can be independently designed, but device complexity increases
Solution Approach 1:
The patent combines alignment and overlay mark functions into a single integrated mark structure, reducing the overall system complexity. Instead of requiring separate measurement procedures and multiple tools, the integrated mark enables both alignment and overlay measurements to be performed by a single measurement system, simplifying the manufacturing process while maintaining design flexibility.
Data Source
AI summary
An integrated alignment and overlay mark includes a pre-layer pattern for reticle-to-wafer registration implemented in an exposure tool, and a current-layer pattern incorporated with the pre-layer pattern. The pre-layer pattern and the current-layer pattern constitute an overlay mark for determining registration accuracy between two patterned layers on a semiconductor wafer.