Integrated Antenna Package for Millimeter-Wave RF Chips
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Solution Overview
Problem
Traditional packaging methods for millimeter-wave radio-frequency (RF) chips, such as wire-bonding and low temperature co-fired ceramic (LTCC) and flip-chip packages, face issues with substrate shrinkage, low process efficiency, and small pad sizes, leading to unsatisfactory yields and signal transmission loss.
Innovation Solution
An integrated antenna package structure is developed with a vertical arrangement of the antenna pattern above or below the RF chip, using a multilayer board with metal via structures to electrically connect the chip and antenna pattern, reducing signal transmission loss by shortening the signal path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional wire-bonding packages are used for RF chips, then the packaging process is simple, but the package is not suitable for RF chip packaging due to signal transmission loss
Solution Approach 1:
The patent combines the RF chip, antenna pattern, and connection structures into a single integrated package substrate. The chip and antenna are co-packaged on the same substrate with direct electrical connections, eliminating the need for separate wire-bonding processes and reducing signal transmission loss while maintaining manufacturing simplicity.
Solution Approach 2:
The patent transitions from traditional planar wire-bonding connections to vertical three-dimensional connections using plated vias through the substrate. The antenna pattern is positioned vertically above or below the chip, creating direct vertical electrical pathways that shorten the signal transmission path and improve RF performance.
2Adaptability or versatility
If LTCC and flip-chip packages are used, then the process capability is advanced, but substrate shrinkage and small pad sizes lead to low yield
Solution Approach 1:
The patent employs different material properties and structural characteristics in different regions of the package. The antenna pattern uses specific trace geometries and impedance control in certain areas, while the chip connection area uses optimized pad and via structures, allowing each region to be optimized for its specific function and improving overall yield.
Solution Approach 2:
The antenna pattern and connection structures are pre-formed on the package substrate before chip mounting. The plated vias and metal traces are created in advance, allowing for better process control and reducing the complexity of subsequent chip assembly steps, thereby improving manufacturing yield.
3Device complexity
If conventional package structures are used, then the design is simple, but the signal transmission path is long causing signal loss
Solution Approach 1:
The patent utilizes vertical three-dimensional connections through plated vias to create direct electrical pathways from the chip contact pads to the antenna pattern. This vertical routing through the substrate dramatically shortens the signal transmission path compared to traditional planar connections, reducing signal loss while maintaining a relatively simple overall package design.
Solution Approach 2:
By integrating the antenna pattern directly onto the package substrate in close proximity to the chip, and using direct plated via connections, the patent merges the RF signal path into a compact integrated structure. This eliminates intermediate connection elements and reduces the overall signal transmission distance, lowering energy loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The integrated antenna package structure achieves a 37.5% reduction in signal transmission loss compared to conventional packages, improving the performance for millimeter-wave applications by using metal via-filled structures within the boreholes for electrical connections.
Implementation Method 1
A plated via structure is then formed in the through-hole and the plated via structure connects the third metal layer and the first contact pad. The antenna pattern is electrically coupled to the chip through the plated via structure.
Data Source
AI summary
An integrated antenna package including a laminated structure and a multi-layered substrate is provided. The laminated structure includes at least a chip embedded therein and at least a plated through-hole structure penetrating the laminated structure. The multi-layered substrate is stacked on the laminated structure. The multi-layered substrate includes at least a metal layer located on one side of the multi-layered substrate away from the laminated structure and the metal layer includes at least an antenna pattern located above the chip. The multi-layered substrate includes at least a plated via and through-hole structure penetrating the multi-layered substrate and electrically connected to the chip, so that the antenna pattern is electrically connect with the chip. Also, the manufacturing method of the integrated antenna package is provided.