Integrated Antenna Semiconductor Device with Cavity

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current semiconductor device packaging faces challenges in reducing cost while meeting performance and reliability expectations, particularly in efficiently transmitting and receiving high-frequency radio frequency signals.

Innovation Solution

A compact semiconductor device is designed with an integrated antenna, where a base die and cap die are bonded together, featuring a metal trace as an integrated antenna interconnected via a conductive via, and a cavity optimized for signal propagation, allowing for shorter signal line lengths and higher frequency transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If conventional packaging methods are used, then manufacturing cost is reduced, but RF transmission loss increases and signal frequency is limited

Engineering Contradiction:
ImproveRF transmission lossVSAvoidmanufacturing cost
Core Design Contradiction:
Loss of energyVSEase of manufacture

Solution Approach 1:

The patent merges the antenna function with the packaging structure by integrating a metal trace antenna directly into the cap die, combining two previously separate functions (antenna and packaging) into a single integrated structure, thereby reducing RF transmission loss while maintaining manufacturing efficiency

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent transitions from planar signal transmission to three-dimensional signal propagation by creating a cavity structure that enables vertical signal paths and optimized electromagnetic field distribution, improving RF performance without increasing manufacturing complexity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Speed

If conventional packaging structures are used, then device complexity is reduced, but signal frequency transmission capability is limited

Engineering Contradiction:
Improvesignal frequencyVSAvoidpackaging structure complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent introduces a three-dimensional cavity structure within the cap die that enables optimized electromagnetic wave propagation paths, allowing higher frequency signals to be transmitted effectively while maintaining a compact form factor that does not significantly increase overall device complexity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent optimizes the physical parameters of the cavity structure (dimensions, position, and configuration) to resonate at and efficiently transmit high-frequency signals greater than 100 GHz, transforming the packaging structure from a simple protective enclosure to an active RF performance enhancement component

Inventive Principle:
Principle #35Parameter changes

3Loss of energy

If signal line length is reduced, then RF transmission loss is reduced, but manufacturing precision requirements increase

Engineering Contradiction:
ImproveRF transmission lossVSAvoidsignal line precision
Core Design Contradiction:
Loss of energyVSManufacturing precision

Solution Approach 1:

The patent combines the antenna trace formation with the existing packaging fabrication process, using the same metal deposition and patterning steps that are already part of the manufacturing flow, thereby achieving short signal paths without imposing additional precision requirements on the manufacturing process

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11705410B2Semiconductor device having integrated antenna and method therefor
Publication Date: 2023.07.18 NXP USA INC
  • US11705410B2 patent drawing
  • US11705410B2 patent drawing
  • US11705410B2 patent drawing

AI summary

A semiconductor device having an integrated antenna is provided. The semiconductor device includes a base die having an integrated circuit formed at an active surface and a cap die bonded to the backside surface of the base die. A metal trace is formed over a top surface of the cap die. A cavity is formed under the metal trace. A conductive via is formed through the base die and the cap die interconnecting the metal trace and a conductive trace of the integrated circuit.