Integrated Capacitive Element With Vertical Trench Structure
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Solution Overview
Problem
Conventional MOS capacitive elements in integrated circuits suffer from high leakage currents and low capacitive value per unit surface area, with design constraints due to polarization issues and 'latch-up' phenomena, limiting their compactness and flexibility.
Innovation Solution
An integrated circuit design featuring a first doped semiconductor well with a second doped well of opposite conductivity, forming a vertical conductive structure within a trench that penetrates into the second well, creating a PMOS device for inversion mode operation, thus avoiding 'latch-up' and increasing capacitive value per unit area without additional surface area or production steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional MOS capacitive element is used, then the production cost is low, but the leakage current is high and the capacitive value per unit surface area is low
Solution Approach 1:
The patent embeds a second doped well (N-type) inside the first doped well (P-type), creating a nested structure where the inner well serves as the capacitive element. This nesting allows the capacitive element to be formed within the existing transistor well structure without requiring additional dedicated production steps, thereby maintaining low production cost while achieving low leakage current through the dual-well configuration that enables inversion mode operation
Solution Approach 2:
The patent transitions from a planar capacitive structure to a vertical three-dimensional structure by forming the capacitive element through depth into the substrate using stacked doped wells. The vertical conductive structure extends through the first well into the second well, utilizing the vertical dimension to increase the effective capacitive area without increasing the surface footprint, thereby achieving higher capacitive value per unit surface area
2Ease of manufacture
If a conventional MOS capacitive element is used, then the production process is simple, but the capacitive value per unit surface area is low
Solution Approach 1:
The patent embeds a second doped well (N-type) inside the first doped well (P-type), creating a nested structure where the inner well serves as the capacitive element. This nesting allows the capacitive element to be formed within the existing transistor well structure without requiring additional dedicated production steps, thereby maintaining low production cost while achieving low leakage current through the dual-well configuration that enables inversion mode operation
Solution Approach 2:
The patent transitions from a planar capacitive structure to a vertical three-dimensional structure by forming the capacitive element through depth into the substrate using stacked doped wells. The vertical conductive structure extends through the first well into the second well, utilizing the vertical dimension to increase the effective capacitive area without increasing the surface footprint, thereby achieving higher capacitive value per unit surface area
3Stability of the object's composition
If the semiconductor well is polarized to achieve inversion mode, then the stability in voltage of the capacitive value is superior, but the latch-up phenomenon occurs due to positioning constraints
Solution Approach 1:
The patent embeds a second doped well (N-type) inside the first doped well (P-type), creating a nested structure where the inner well serves as the capacitive element. This nesting allows the capacitive element to be formed within the existing transistor well structure without requiring additional dedicated production steps, thereby maintaining low production cost while achieving low leakage current through the dual-well configuration that enables inversion mode operation
Solution Approach 2:
The patent introduces a vertical conductive structure (N-type) as an intermediary element that extends through the first P-type well into the second N-type well. This vertical structure acts as a mediator that enables control of the capacitive element through inversion mode while being electrically isolated by the dielectric envelope, thereby achieving stable voltage characteristics without inducing latch-up phenomena in the surrounding P-type wells
4Area of stationary object
If a compact capacitive element is designed, then the capacitive value per unit surface area is high, but the leakage current increases
Solution Approach 1:
The patent embeds a second doped well (N-type) inside the first doped well (P-type), creating a nested structure where the inner well serves as the capacitive element. This nesting allows the capacitive element to be formed within the existing transistor well structure without requiring additional dedicated production steps, thereby maintaining low production cost while achieving low leakage current through the dual-well configuration that enables inversion mode operation
Solution Approach 2:
The patent transitions from a planar capacitive structure to a vertical three-dimensional structure by forming the capacitive element through depth into the substrate using stacked doped wells. The vertical conductive structure extends through the first well into the second well, utilizing the vertical dimension to increase the effective capacitive area without increasing the surface footprint, thereby achieving higher capacitive value per unit surface area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables compact, high-capacitive integrated capacitive elements with minimal leakage and flexible positioning, achieving superior stability in inversion mode and increased capacitive value without increasing surface area or production complexity.
Implementation Method 1
The second well serves as a source of minority carriers in the first well, to enable an inversion mode
Implementation Method 2
the vertical conductive structure forms a PMOS type device suitable for inducing a conduction channel region in the first well
Implementation Method 3
the vertical conductive structure being electrically isolated from the first well by a dielectric envelope covering the base and the sides of said trench
Implementation Method 4
the second well is isolated particularly from the semiconductor substrate and from the other P-type wells by PNP double junctions
Data Source
AI summary
An integrated circuit includes a first semiconductor well contained in a semiconductor substrate and a second semiconductor well contained in the first semiconductor well. A capacitive element for the integrated circuit includes a first electrode and a second electrode, where the first electrode includes at least one vertical conductive structure filling a trench extending vertically into the first semiconductor well. The vertical conductive structure is electrically isolated from the first semiconductor well by a dielectric envelope covering a base and the sides of the trench. The vertical conductive structure penetrates into the second semiconductor well at least at one longitudinal end of the trench. The second electrode includes the first semiconductor well and the second semiconductor well.