Integrated Capacitor Basket-Weave Segmentation
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Solution Overview
Problem
Integrated capacitors in ICs face challenges in achieving high capacitance per unit area, low loss, and low self-inductance, which are crucial for high-frequency applications, as existing designs often result in undesirable inductance-resistance profiles and inefficient use of surface area.
Innovation Solution
The capacitor design features a basket-weave pattern with node plate links in multiple metal layers connected by vias, providing both inter-layer and intra-layer capacitance, and using a polysilicon or silicide layer to enhance capacitance while minimizing inductive and resistive impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple conductive plates are used to increase capacitance per unit area, then capacitance increases, but device complexity increases
Solution Approach 1:
The capacitor structure is segmented into multiple conductive plates (first conductive plate, second conductive plate, third conductive plate) separated by dielectric layers. Each plate segment contributes to the total capacitance, allowing the capacitor to achieve high capacitance per unit area by dividing the capacitive structure into discrete, manageable segments rather than using a single large plate
Solution Approach 2:
The capacitor structure employs a nested arrangement where conductive plates and dielectric layers are stacked vertically one on top of another. The first conductive plate is positioned at a first level, the second conductive plate at a second level, and the third conductive plate at a third level, with dielectric layers interspersed between them. This nesting approach maximizes the use of vertical space to increase capacitance without proportionally increasing the horizontal footprint
2Quantity of substance
If long parallel conductive fingers are used, then capacitance increases, but self-inductance increases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of conductive fingers to a three-dimensional stacked arrangement of conductive plates separated by dielectric layers. By utilizing the vertical dimension (z-axis) with multiple levels of conductive plates, the design achieves increased capacitance without requiring long horizontal conductive paths, thereby reducing self-inductance
3Reliability
If conductive strips are offset a half cell on successive layers, then coupling balance is improved, but capacitance per unit area decreases
Solution Approach 1:
The patent employs an asymmetric arrangement where the third conductive plate is positioned to overlap with the first conductive plate in the vertical direction, rather than offsetting it by a half cell. This asymmetric positioning allows the third conductive plate to maximize its overlapping area with the first conductive plate through the intervening dielectric layer, thereby increasing the capacitance per unit area while maintaining acceptable coupling balance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves high specific capacitance with low inductive and resistive impedance, increasing the self-resonant frequency and quality of capacitor circuits, making it suitable for various applications including filtering, switching, and RF coupling.
Implementation Method 1
A first dielectric material is formed over the first conductive plate and underlying second conductive plate
Implementation Method 2
Capacitors are used in IC systems for a variety of purposes
Data Source
Figure 1A~1B
Figure 1C~2A
Figure 2B~2E
AI summary
A capacitor (100) in an integrated circuit ("IC") has a first node plate link (102) formed in a first metal layer of the IC electrically connected to and forming a portion of a first node of the capacitor extending along a first axis (y) and a second node plate link (108) formed in a second metal layer of the IC extending along the axis and connected to the first node plate with a via (112). A third node plate link (106) formed in the first metal layer is electrically connected to and forming a portion of a second node of the capacitor and extends along a second axis (x) of the node plate array transverse to the first node plate link, proximate to an end of the first node plate link and overlying a portion of the second node plate link.