Integrated Capacitor Conductive Crosses High Density
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Solution Overview
Problem
Integrated capacitors in ICs face challenges in achieving high specific capacitance per unit area, low loss, and low self-inductance while maintaining manufacturability and quality factor, with issues related to surface area consumption, substrate coupling, and variability in capacitance value across ICs, wafers, and lots.
Innovation Solution
The design incorporates a plurality of conductive crosses in metal layers electrically connected to form nodes, with overlapping patterns and perimeter shields to enhance lateral capacitance, minimize substrate coupling, and maintain small feature sizes for high fill-factor and reliable manufacturing, using techniques like damascene and dual damascene processes for via formation and metal trace creation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple conductive strips are used to increase capacitance, then specific capacitance per unit area is improved, but device complexity increases
Solution Approach 1:
The capacitor structure is segmented into multiple conductive strips arranged in alternating layers, with each layer containing multiple strips connected to different nodes. This segmentation allows capacitance to be distributed across multiple elements rather than requiring a single large structure, thereby increasing specific capacitance while managing complexity through modular arrangement.
Solution Approach 2:
The patent transitions from planar capacitor structures to three-dimensional stacked configurations with conductive strips in multiple layers. By utilizing the vertical dimension and stacking layers above each other with alternating node connections, the capacitance density increases significantly without proportionally increasing the footprint area, thus improving specific capacitance while controlling overall device complexity.
2Stability of the object's composition
If conductive strips are offset a half cell on successive layers to balance substrate coupling, then coupling balance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs asymmetric offset positioning where conductive strips in successive layers are shifted by half a cell distance relative to each other. This asymmetric arrangement creates alternating patterns of strong and weak coupling regions, achieving balanced overall substrate coupling. The systematic asymmetric design provides manufacturing tolerance compared to requiring precise symmetric alignment.
3Area of stationary object
If overlapping conductive strips connected to the same node are used, then surface area is reduced, but inter-layer capacitance decreases
Solution Approach 1:
The patent implements a dynamic alternating connection scheme where conductive strips in overlapping regions are connected to different nodes in successive layers. Rather than maintaining a static connection pattern, the design dynamically alternates which node each strip connects to based on its layer position, thereby maintaining charge separation and preserving inter-layer capacitance while achieving compact overlapping geometry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves high specific capacitance per unit area, reduces substrate coupling, and ensures consistent capacitance values, improving high-frequency applications and manufacturability by optimizing lateral capacitance and minimizing surface area usage.
Implementation Method 1
capacitively couple to the first node
Implementation Method 2
each conductive plate separated from the proximate plate(s) by dielectric
Data Source
Figure 1A~2B
Figure 2A~2C
Figure 3A~4
AI summary
A capacitor (100) in an integrated circuit ("IC") has a first plurality of conductive crosses (102, 104) formed in a layer of the IC electrically connected to and forming a portion of a first node of the capacitor and a second plurality of conductive crosses (108, 110) formed in the metal layer of the IC. The conductive crosses in the second plurality of conductive crosses are electrically connected to and form a portion of a second node of the capacitor and capacitively couple to the first node.