Integrated Capacitor Structure Using Pillar-Supported Selective Etching
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Solution Overview
Problem
Existing methods for fabricating capacitors peripheral to memory arrays in integrated circuitry face challenges such as structural collapse during the removal of insulative material, leading to inefficiencies and increased costs.
Innovation Solution
A method involving the partial removal of insulative material to form insulative pillars that support the remaining structure, followed by deposition of conductive material to create capacitive stacks, utilizing gate replacement methodology similar to memory cell fabrication, thereby reducing fabrication steps and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If insulative material is completely removed to form capacitive structures, then capacitor fabrication is achieved, but structural collapse occurs during the removal process
Solution Approach 1:
The insulative material removal process is segmented into selective removal steps where only specific portions of the insulative material are removed at different stages. This allows the structure to maintain stability during fabrication while still forming the required capacitive regions through controlled, incremental material removal.
Solution Approach 2:
Support structures are formed preliminarily before the insulative material removal process begins. These support structures are strategically positioned to prevent collapse during the subsequent removal operations, ensuring structural integrity is maintained throughout the capacitor fabrication process.
2Reliability
If separate fabrication processes are used for memory cells and capacitors, then each component can be optimized independently, but fabrication time and costs increase
Solution Approach 1:
The fabrication processes for memory cells and capacitors are merged into a unified process flow. Common process steps including insulative material deposition, pattern formation, and selective removal are combined and executed sequentially for both component types, reducing total fabrication time and operational costs while maintaining the ability to independently optimize each component's final structure.
Solution Approach 2:
The fabrication methodology is designed to be universal, applying the same core process steps and material systems to both memory cell and capacitor fabrication. This multi-functional approach allows a single process platform to produce different device types, improving overall fabrication efficiency without sacrificing component-specific optimization capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents structural collapse and reduces fabrication time and costs by using common materials and processes for both memory cells and capacitors, enhancing the integration of capacitors in integrated circuitry.
Implementation Method 1
The second insulative material is exhumed with etchant provided in the slots to form voids within the second levels
Implementation Method 2
The voids are filled with conductive material, and the conductive material is formed into conductive plates within the second levels
Data Source
AI summary
Some embodiments include an integrated structure having a semiconductor base and an insulative frame over the semiconductor base. The insulative frame has vertically-spaced sheets of first insulative material, and pillars of second insulative material between the vertically-spaced sheets. The first and second insulative materials are different from one another. Conductive plates are between the vertically-spaced sheets and are directly against the insulative pillars. Some embodiments include capacitors, and some embodiments include methods of forming capacitors.