Integrated Chip Package Structure for Thinner High-Density Modules
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Solution Overview
Problem
Conventional chip package structures using plastic or ceramic substrates face challenges in achieving a sufficiently thin and compact size, which hinders high-density integration due to their thickness and bulkiness.
Innovation Solution
A chip package structure is developed with a substrate having a wiring layer directly formed on it, where metal wires contact the substrate and overlap the second region, allowing the chip to be connected via conductive bumps for signal transmission, eliminating the need for additional bases and adhesive layers, thus reducing thickness and size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If conventional chip package structures use plastic or ceramic substrates with bases and adhesive layers, then structural stability is improved, but package thickness and size increase
Solution Approach 1:
The patent merges the substrate and wiring layer into a single integrated structure. The wiring layer is directly formed on the substrate through film forming processes, eliminating the need for separate base structures and adhesive layers. This integration maintains structural stability while significantly reducing package thickness and size.
Solution Approach 2:
The invention extracts and removes unnecessary intermediate layers from the conventional package structure. By eliminating the base and adhesive layers that are typically required in plastic or ceramic packages, the design achieves direct mounting of the chip on the substrate, thereby reducing overall thickness while maintaining structural integrity through the integrated wiring layer.
2Strength
If additional bases and adhesive layers are used in conventional packaging, then mechanical support is improved, but device complexity and manufacturing steps increase
Solution Approach 1:
The substrate and wiring layer are combined into a single integrated component. The wiring layer is directly formed on the substrate using film forming processes, creating a unified structure that provides both mechanical support and electrical connectivity. This eliminates the need for separate base structures and adhesive layers, reducing device complexity and manufacturing steps.
3Ease of manufacture
If conventional packaging methods are used, then ease of manufacture is maintained, but high-density integration is hindered due to larger size
Solution Approach 1:
The integrated substrate-wiring layer structure maintains ease of manufacture by using standard film forming processes while achieving compact dimensions. The direct formation of wiring layers on the substrate eliminates the need for additional assembly steps involving separate bases and adhesives, keeping manufacturing simple while enabling high-density integration through reduced package size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a lighter, thinner chip package that simplifies manufacturing and supports high-density integration by eliminating the need for additional bases and adhesive layers, enhancing signal transmission efficiency and imaging quality.
Implementation Method 1
the wiring layer includes at least one metal wire, at least part of one of the at least one metal wire is in contact with the substrate, and the at least one metal wire overlap with the second region
Implementation Method 2
the first conductive bump is electrically connected to one of the at least one metal wire, the second conductive bump is electrically connected to one of the at least one metal wire
Data Source
AI summary
A chip package structure, manufacturing method thereof, and module are described. In an embodiment, the chip package structure includes: a substrate, a wiring layer, a chip, and a second conductive bump, wherein, in an embodiment, the substrate includes a first region and a second region surrounding the first region, and the wiring layer is located on side of the substrate and includes metal wire, wherein at least part of a metal wire is in contact with the substrate in direction perpendicular to the substrate, and the metal wire overlaps with the second region, wherein the chip is located on side of the wiring layer facing away from the substrate, and the chip corresponds to the first region. In an embodiment, a first conductive bump is provided on side of the chip facing away from the substrate and is electrically connected to the metal wire.