Integrated Circuit Back-Side Routing for Supply Integrity
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Solution Overview
Problem
Integrated circuits face challenges with power supply potential fluctuations due to high resistivity interconnects, excessive IC real estate consumption by ESD protection, and inefficient routing, which affect circuit compactness and functionality.
Innovation Solution
The integration of first and second rows of insulated gate field effect transistors (IGFETs) on one side of the IC device, with conductive signal paths and power supply connections via vias and conductive structures, enhancing supply potential integrity and routing efficiency while incorporating ESD protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional power supply routing is used, then power supply connections can be established, but supply potential integrity deteriorates due to high resistivity interconnect
Solution Approach 1:
The patent utilizes the back side of the substrate to route power supply voltages, transitioning from planar routing to three-dimensional routing. Through-holes penetrate the substrate to connect back side routing to front side circuits, effectively reducing the length and resistance of power supply interconnects while improving supply potential integrity.
Solution Approach 2:
The patent divides power supply routing into separate dedicated paths on the back side of the substrate, with first and second power supply voltages routed through distinct through-holes and conductive structures. This segmentation reduces interference and resistance in each individual power supply path.
2Reliability
If ESD protection circuits are added, then electrostatic discharge protection is improved, but IC real estate consumption increases
Solution Approach 1:
The patent integrates ESD protection circuits with the back side power supply routing structure. The ESD protection circuits share the back side substrate area and routing infrastructure with power supply connections, thereby providing comprehensive protection while minimizing additional area consumption.
Solution Approach 2:
ESD protection circuits are placed on the back side of the substrate and connected through the same through-holes used for power supply routing. This vertical integration reduces the planar area required for ESD protection while maintaining effective protection functionality.
3Productivity
If traditional routing is used, then signal connections can be established, but routing efficiency deteriorates and IC real estate is excessively consumed
Solution Approach 1:
The patent routes signal connections through the back side of the substrate using through-holes, transitioning from two-dimensional planar routing to three-dimensional routing. This approach significantly reduces the area required for routing while improving signal connection efficiency and reducing interference with front side active devices.
Data Source
AI summary
A method can include receiving a first and second power supply voltage at first and second terminals. An input signal can be received at, or an output signal provided on a third terminal. First and second rows of insulated gate field effect transistors (IGFETs) can be provided at a second side of an IC device, and can form a circuit. A conductive signal path can be provided between the third terminal and the circuit via a third via and third conductive structure. Corresponding devices and systems are also disclosed.