Integrated Circuit Layout With Backside Routing for RC Delay
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Solution Overview
Problem
As semiconductor integrated circuits scale down, backend metal layers face limitations in resistance and capacitance, leading to RC delay and IR drop issues that hinder performance and scaling, particularly in GAA transistor era where BEOL routing efficiency becomes a bottleneck.
Innovation Solution
The implementation of frond-side source node connection and back-side drain node connection configurations in integrated circuit structures to reduce contact resistance and capacitance, respectively, thereby improving cell/device density and performance by optimizing metal routing and SID connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional transistor scaling is pursued, then functional density increases, but RC delay and IR drop worsen due to backend metal layer limitations
Solution Approach 1:
The patent introduces a third dimension by forming contacts through the substrate from the back surface to the front surface. This vertical through-substrate routing adds a new spatial dimension for electrical connections, bypassing the limitations of planar backend metal layers and reducing RC delay and IR drop while maintaining high functional density.
Solution Approach 2:
The patent segments the interconnection path by separating the routing into two parts: lateral connections on the front surface and vertical through-substrate connections. This segmentation allows optimization of each segment independently, with the vertical segment providing low-resistance power delivery and the lateral segment providing flexible signal routing.
2Reliability
If backend metal routing is optimized, then signal transmission improves, but device complexity increases
Solution Approach 1:
The patent extracts the power delivery function from the planar metal routing system by implementing vertical through-substrate contacts. This separates power transmission (handled by vertical contacts) from signal routing (handled by lateral metal lines), simplifying the overall routing architecture and reducing the complexity of backend metal layers.
Solution Approach 2:
The through-substrate contacts act as intermediaries that connect the front surface device region to the back surface interconnection layer. This intermediary structure provides a low-resistance pathway for power delivery while allowing the front surface metal routing to focus on signal transmission, thereby improving signal quality without proportionally increasing complexity.
3Reliability
If contact resistance is reduced, then power transmission efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary patterning of the through-substrate contacts on the back surface before substrate thinning and front surface processing. This preliminary action establishes the contact positions and dimensions early in the fabrication sequence, allowing subsequent steps to align to these pre-defined features and reducing the cumulative precision requirements.
Solution Approach 2:
The patent incorporates a contact etch stop layer that provides a predefined termination point for the through-substrate contact etching process. This cushioning feature ensures that even with variations in substrate thickness or etching conditions, the contacts will not etch through the substrate completely, providing a margin of error that reduces the stringency of manufacturing precision requirements.
Data Source
AI summary
A semiconductor device includes a substrate, a dielectric fin, a gate, and a high-k dielectric layer. The dielectric fin is above the substrate and extending along a first direction. The gate is above the substrate and extends in a second direction that intersects the first direction. The high-k dielectric layer is vertically above the dielectric fin. The gate is over a sidewall and a bottom surface of the high-k dielectric layer.