Integrated Circuit Dual-Gate FET for Charge-Trapping Threshold Programming
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Solution Overview
Problem
The integration of diverse electronic components and transistor structures on a single chip poses challenges in achieving high functional density and efficient programming of threshold voltage in semiconductor devices.
Innovation Solution
A dual-gate FET device with a programming gate structure and a switching gate structure is developed, featuring a charge-trapping layer and a data storage layer to programmably alter the threshold voltage, allowing for non-volatile memory storage elements with independent gate biasing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple diverse electronic components and transistor structures are integrated on a single chip to increase functional density, then the quantity of components increases, but the complexity of forming and integrating these components increases
Solution Approach 1:
The patent implements a dual-gate FET structure where the first gate structure serves as a switching gate and the second gate structure serves as a programming gate. This multi-functional design allows a single transistor structure to perform both switching operations and threshold voltage programming, thereby increasing functional density without proportionally increasing device complexity
Solution Approach 2:
The patent divides the gate control function into two separate gate structures: a first gate structure for switching control and a second gate structure for threshold voltage programming. This segmentation allows independent optimization of switching performance and programming capability, simplifying the integration process for diverse functional blocks
2Adaptability or versatility
If a charge-trapping layer and data storage layer are added to enable programmable threshold voltage, then the adaptability of the device increases, but the device complexity increases
Solution Approach 1:
The patent implements a nested gate structure where the second gate structure (programming gate) is positioned over the first gate structure (switching gate), with the charge-trapping layer and data storage layer situated between them. This nested configuration allows the programming function to be integrated within the existing switching gate structure, adding adaptability while minimizing increases in overall device complexity
Solution Approach 2:
The patent adds vertical layering with the charge-trapping layer and data storage layer positioned between the two gate structures, utilizing the vertical dimension to accommodate additional functionality. This dimensional approach allows threshold voltage programming capability to be added without significantly increasing the lateral footprint or planar complexity of the device
3Measurement precision
If independent gate biasing is implemented for programming and switching gates, then the precision of threshold voltage control improves, but the ease of operation decreases
Solution Approach 1:
The patent introduces a tunneling layer as an intermediary between the first gate structure and the charge-trapping layer. This tunneling layer facilitates controlled charge transfer during programming operations while isolating the switching gate from programming voltages, thereby enabling precise threshold voltage control without requiring complex simultaneous biasing of both gates
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device enables multiple stable charged states with negligible charge leakage, facilitating efficient programming and reading of threshold voltage, suitable for high-density integrated circuits.
Implementation Method 1
featuring a charge-trapping layer and a data storage layer to programmably alter the threshold voltage
Implementation Method 2
The bottom layer may be referred to as a tunneling layer, which includes an insulator (e.g., an oxide) which may be sufficiently thin to allow charge transport through of the dielectric by electron tunneling
Data Source
AI summary
An integrated circuit device includes a semiconductor substrate, a first gate structure, a channel layer, source and drain features, a second gate structure, a first contact, and a second contact. The first gate structure is over the semiconductor substrate. The first gate structure includes a gate dielectric layer and a first gate electrode. The channel layer is over and surrounded by the first gate structure. The source and drain features are respectively on opposite first and second sides of the channel layer. The second gate structure is over the channel layer. The second gate structure includes a programming gate dielectric layer having a data storage layer and a second gate electrode over the programming gate dielectric layer. The first gate contact is on the first gate electrode. The second gate contact is on the second gate electrode.