Integrated Circuit Backside Gate Partial Cuts for Capacitance Reduction
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Solution Overview
Problem
The challenge of scaling multi-gate transistors below the 10 nanometer node is hindered by constraints on lithographic processes, leading to trade-offs between feature dimension and spacing, which affects device performance and capacitance.
Innovation Solution
Implementing a backside gate partial cut or trench contact partial cut, along with spit epitaxial structure, using sub-fin self-aligned processes to reduce device capacitance and improve scaling by selectively removing gate metal and epitaxial structures from the backside of integrated circuit structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistors are scaled below the 10 nanometer node, then device density and capacity are increased, but lithographic process constraints become overwhelming and trade-offs between critical dimension and feature spacing occur
Solution Approach 1:
The patent applies backside processing to remove gate metal and epitaxial structures from the rear surface of the substrate, transitioning from conventional front-side processing to dual-sided processing. This dimensional approach enables capacitance reduction without additional front-side lithographic complexity, allowing aggressive scaling while managing process constraints through backside intervention
2Productivity
If device dimensions are reduced to increase capacity, then more devices fit on the chip, but maintaining mobility improvement and short channel control becomes increasingly difficult
Solution Approach 1:
The patent extracts and removes portions of the gate metal structure from the backside of the device, specifically removing gate metal in regions where it would contribute to parasitic capacitance. This extraction reduces capacitance without compromising the essential gate control function, enabling scaled devices to maintain electrical characteristics despite reduced dimensions
Solution Approach 2:
The backside gate partial cut process applies selective removal of gate metal to specific local regions where capacitance reduction is needed, rather than uniformly removing all gate metal. This localized approach maintains gate control functionality in critical areas while eliminating parasitic capacitance in other regions, preserving device performance at scaled dimensions
3Ease of manufacture
If conventional front-side processing is used for tri-gate transistors, then fabrication process is simpler, but capacitance management and performance optimization are limited
Solution Approach 1:
The patent inverts the conventional processing approach by performing gate metal removal and epitaxial structure modification from the backside rather than the front side. This inversion enables capacitance management that would be difficult or impossible to achieve with conventional front-side processing, as the backside access allows direct removal of gate metal in capacitance-critical regions without disrupting front-side device structures
Data Source
AI summary
Integrated circuit structures having backside gate partial cut or backside trench contact partial cut and/or spit epitaxial structure are described. For example, an integrated circuit structure includes a first sub-fin structure over a first stack of nanowires. A second sub-fin structure is over a second stack of nanowires. A first portion of a gate electrode is around the first stack of nanowires, a second portion of the gate electrode is around the second stack of nanowires, and a third portion of the gate electrode bridges the first and second portions of the gate electrode. A dielectric structure is between the first portion of the gate electrode and the second portion of the gate electrode, the dielectric structure over the third portion of the gate electrode. The dielectric structure is continuous along the first and second portions of the gate electrode and the first and second sub-fin structures.