Integrated Circuit Layout Leakage Detection Before Post-Layout Simulation
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Solution Overview
Problem
The challenge in integrated circuit (IC) design is the inefficiency in identifying and addressing leakage violations caused by dummy gate regions, which can affect circuit performance and require extensive debugging during post-layout simulations.
Innovation Solution
A method is introduced to perform an automated leakage test on the netlist, flagging leakage-sensitive schematic nets and modifying the IC layout diagram to address leakage violations before post-layout simulation, using a capacitance-only netlist extraction to verify circuit performance without dummy gate regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If dummy gate regions are added to the IC layout diagram, then manufacturing process optimization is improved, but leakage violations occur affecting circuit performance
Solution Approach 1:
The patent performs leakage detection during the layout design phase, before post-layout simulation, by analyzing the netlist and identifying leakage-sensitive schematic nets. This preliminary action allows dummy gate regions to be strategically placed or modified to prevent leakage violations before they affect circuit performance, thus resolving the contradiction between manufacturing optimization and reliability.
2Measurement precision
If post-layout simulation is performed to detect leakage violations, then circuit performance verification is improved, but extensive debugging time is required
Solution Approach 1:
The patent implements leakage detection during the layout design phase, extracting netlist information and identifying leakage-sensitive nets before post-layout simulation. This preliminary leakage check allows designers to address potential issues early, reducing the need for extensive debugging during later simulation phases while maintaining verification precision.
Solution Approach 2:
The system automatically analyzes the netlist and identifies leakage-sensitive schematic nets without requiring manual intervention. The automated leakage detection process serves itself by using the extracted netlist data to flag potential leakage issues, reducing the time burden on designers while maintaining accurate circuit performance verification.
3Productivity
If automated leakage testing is implemented, then design efficiency is improved, but additional analysis steps are added to the process
Solution Approach 1:
The patent merges the leakage detection process with the existing netlist extraction and layout design workflow. By integrating leakage analysis into the automated place-and-route process, the system performs additional analysis without significantly increasing process complexity. The leakage-sensitive net identification is combined with standard design procedures, improving productivity while maintaining process simplicity.
Data Source
AI summary
An integrated circuit (IC) layout diagram generation system includes a processor and a non-transitory, computer readable storage medium including computer code for one or more programs. The non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, cause the processor to generate a layout diagram of an IC device by performing a capacitance-only netlist extraction on an IC layout diagram, obtaining a first simulation result based on the extracted netlist, revising the extracted netlist by removing the dummy gate region, obtaining a second simulation result based on the revised netlist, and comparing the first simulation result to the second simulation result to determine a leakage-based design impact.