Integrated Circuit Power Fill Layout for DRC Spacing Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The addition of power fill to integrated circuit layouts causes significant layout design rule check (DRC) physical verification errors due to increased metal line spacing, which is time-consuming and inefficient to manually correct.
Innovation Solution
A method and apparatus for automatically correcting DRC spacing errors by iteratively pruning power fill meshes in real-time, classifying error types, and adjusting power fill shapes to meet minimum spacing requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power fill is added to reduce resistance on power nets, then the equivalent resistance from power pin pad to logic gate cell is reduced, but layout DRC physical verification errors increase
Solution Approach 1:
The power fill mesh is segmented into multiple smaller mesh cells rather than using a single large continuous mesh. This segmentation allows the power fill to reduce resistance effectively while minimizing the generation of DRC errors by distributing the mesh structure across multiple manageable sections that can be independently optimized.
Solution Approach 2:
The power fill mesh density and configuration are adjusted locally in different regions of the layout based on specific DRC error conditions. In regions where DRC errors occur, the mesh structure is modified locally to resolve spacing violations while maintaining the overall resistance-reduction benefit in power-net critical areas.
2Reliability
If power fill meshes are added to reduce resistance, then IR drop on power nets is reduced, but manual correction of DRC errors becomes more time-consuming
Solution Approach 1:
The layout design system automatically detects DRC errors and performs self-correction by adjusting power fill mesh configurations. The system identifies spacing violations and automatically modifies the power fill structure to resolve errors, eliminating the need for manual intervention and significantly reducing correction time while maintaining power net performance.
Solution Approach 2:
The design process incorporates automated feedback loops where DRC verification results are fed back to automatically adjust power fill mesh configurations. This iterative feedback mechanism continuously refines the layout to resolve DRC errors while maintaining the resistance-reduction benefits, eliminating manual correction steps.
3Area of stationary object
If original metal lines are made denser to reduce spacing errors, then layout compactness is improved, but power fill addition becomes more difficult
Solution Approach 1:
The power fill mesh configuration is made dynamic and adaptable to the existing metal line density. The mesh structure automatically adjusts its parameters (such as cell size and distribution) based on the local metal line spacing and DRC error conditions, allowing power fill to be effectively added even in densely packed layouts without causing excessive DRC errors.
Data Source
AI summary
A method and an apparatus of designing an integrated circuit are provided. The method includes: S1, loading a power fill to a circuit layout with original metal lines; S2, checking whether a current layout includes a region with a spacing error; if yes, performing S3; otherwise, outputting the current layout; and S3, pruning a power fill shape corresponding to the region with a spacing error by a predetermined spacing width delta, and returning to the S2.