Integrated Circuit Sub-Fin Isolation via Al2O3-Catalyzed Oxidation

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Solution Overview

Problem

Conventional methods for sub-fin isolation in integrated circuit fabrication face challenges such as non-uniformity and variability in sub-fin isolation thickness due to etch loading effects and plasma damage, leading to degraded device performance and increased process complexity.

Innovation Solution

A low temperature Al2O3-catalyzed silicon oxidation process is employed to uniformly oxidize sub-fin structures, providing self-aligned and pitch-independent isolation, reducing process steps and defects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional etching methods are used for sub-fin isolation, then isolation structures can be formed, but non-uniformity and variability in isolation thickness occur due to etch loading effects and plasma damage

Engineering Contradiction:
Improvesub-fin isolation thickness uniformityVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent replaces the mechanical/physical etching process with a chemical oxidation process. Instead of using plasma etching to remove sub-fin structures, the invention uses thermal oxidation to convert silicon sub-fins to silicon oxide, which provides uniform isolation thickness without etch loading effects or plasma damage to the gate stack.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the fundamental parameter of the isolation formation process from etching (removal of material) to oxidation (conversion of material). This parameter change enables precise control of isolation thickness through oxidation time and temperature, achieving uniformity across different device sizes and patterns while avoiding the variability inherent in etch-based methods.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If etch-based sub-fin isolation is used, then isolation can be achieved, but process steps and defects increase

Engineering Contradiction:
Improvedevice performanceVSAvoidprocess efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent replaces the multi-step etch-based isolation process with a single oxidation step. This substitution eliminates plasma damage to gate stacks, removes the need for complex etch parameter optimization, and reduces the number of process steps while improving device performance through uniform isolation.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The oxidation process is self-limiting and self-aligning. The silicon sub-fins oxidize in situ without requiring additional alignment steps or masking, and the process automatically stops when the desired isolation thickness is achieved, improving productivity by eliminating multiple process steps.

Inventive Principle:
Principle #25Self-service

3Manufacturing precision

If oxidation process is used for sub-fin isolation, then uniform isolation is achieved across diverse device sizes, but process temperature control is required

Engineering Contradiction:
Improveisolation thickness consistencyVSAvoidprocess temperature control
Core Design Contradiction:
Manufacturing precisionVSTemperature

Solution Approach 1:

The patent utilizes the well-established relationship between oxidation temperature, time, and thickness to achieve precise control of isolation dimensions. By controlling oxidation parameters (temperature and time), uniform isolation thickness is achieved across all devices regardless of size or pattern density, with the temperature control being a standard and reliable process parameter.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution achieves consistent sub-fin isolation across diverse device sizes and patterns, enhancing transistor performance by minimizing parasitic capacitance and leakage, while simplifying the process flow and reducing costs.

Implementation Method 1

A low temperature Al2O3-catalyzed silicon oxidation process is employed to uniformly oxidize sub-fin structures

Methodology Applied
Scientific EffectCatalysis: Catalysis

Implementation Method 2

A low temperature Al2O3-catalyzed silicon oxidation process is employed to uniformly oxidize sub-fin structures

Methodology Applied
Scientific EffectOxidation: Oxidation

Data Source

PatentUS20250227993A1Integrated circuit structures with sub-FIN isolation
Publication Date: 2025.07.10 INTEL CORP
  • US20250227993A1 patent drawing
  • US20250227993A1 patent drawing
  • US20250227993A1 patent drawing

AI summary

Integrated circuit structures having sub-fin isolation, and methods of fabricating integrated circuit structures having sub-fin isolation, are described. For example, an integrated circuit structure includes a channel structure, and an oxide sub-fin structure over the channel structure, the oxide sub-fin structure including silicon and oxygen and aluminum.