Integrated Circuit with Thin Body FET and Capacitor
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Solution Overview
Problem
Conventional CMOS fabrication processes for thin body field effect transistors (FETs) result in high resistance capacitors due to the high resistance of the thin body, which affects the performance of integrated circuits.
Innovation Solution
An integrated circuit design that incorporates a fully depleted FET and an on-chip capacitor sharing a high-k dielectric and metal layer, with a low resistance silicide electrode and metal electrode, and a method for forming the capacitor during a trench silicide/contact formation process, allowing for improved electrical characteristics and reduced process complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CMOS fabrication processes are used for thin body FETs, then device characteristics are improved, but capacitor resistance increases
Solution Approach 1:
The patent merges the transistor fabrication process with capacitor formation by integrating the silicide electrode formation step. The silicide layer is deposited and annealed to form low-resistance electrodes for both the transistor source/drain regions and the capacitor electrodes simultaneously, eliminating the high resistance issue while maintaining process compatibility with thin body FETs
Solution Approach 2:
The patent changes the electrical parameters of the capacitor by forming silicide regions (such as cobalt silicide or nickel silicide) on the capacitor electrodes. This material transformation reduces the electrode resistance from high to low, directly addressing the capacitor resistance problem while using standard fabrication parameters
2Reliability
If thin body FETs are used, then device characteristics are improved, but process complexity increases
Solution Approach 1:
The silicide formation process serves multiple functions: it creates low-resistance contacts for the transistor source/drain regions, forms the capacitor electrodes, and provides a unified approach for both device types. This multi-functionality reduces process complexity by eliminating separate fabrication steps for transistors and capacitors
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces the resistance of on-chip capacitors, enhancing their electrical characteristics and simplifying the fabrication process, while being applicable to various devices like finFETs and nanowire devices.
Implementation Method 1
A second high-k dielectric layer is located on the silicide region
Implementation Method 2
The capacitor includes a first terminal that comprises a third silicide region located on a portion of the second semiconductor layer
Data Source
AI summary
An circuit supporting substrate includes a transistor and a capacitor. The transistor includes a first semiconductor layer and a gate stack located on the first semiconductor layer. The gate stack includes a metal layer and a first high-k dielectric layer. A gate spacer is located on sidewalls of the gate stack. The first high-k dielectric layer is located between the first semiconductor layer and the metal layer and between the gate spacer and sidewalls of the metal layer. A first silicide region is located on a first source/drain region. A second silicide region is located on a second source/drain region. The capacitor includes a first terminal that comprises a third silicide region located on a portion of the second semiconductor. A second high-k dielectric layer is located on the silicide region. A second terminal comprises a metal layer that is located on the second high-k dielectric layer.