Integrated Circuit Power Routing With Offset Through-Vias
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Solution Overview
Problem
Integrated circuit (IC) devices face challenges with supply potential integrity, routing efficiency, electrostatic discharge (ESD) protection, and circuit compactness due to high resistivity interconnects and large ESD real estate consumption.
Innovation Solution
The solution involves receiving power supply voltages at terminals on one side of the IC device and distributing them through insulated gate field effect transistors (IGFETs) on the opposite side, using buried conductive lines and through vias to connect the terminals to the IGFETs, thereby improving supply integrity and routing efficiency while compacting the circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power supply voltage is distributed through traditional interconnect structures, then power delivery is achieved, but supply potential integrity deteriorates due to high resistivity
Solution Approach 1:
The patent introduces through-vias that extend vertically through the substrate, adding a third-dimensional routing path for power delivery. This vertical dimension bypasses the high-resistivity planar interconnect layers, providing a low-resistance direct path from bottom-side power pads to top-side circuitry, thereby maintaining supply potential integrity.
Solution Approach 2:
The power distribution network is segmented into multiple parallel conductive paths consisting of through-vias and embedded conductive lines. This segmentation divides the current load across multiple low-resistance pathways, reducing overall resistivity and voltage drop, thus improving supply potential integrity.
2Adaptability or versatility
If traditional power and signal routing is used, then circuit functionality is achieved, but IC real estate is consumed excessively
Solution Approach 1:
By utilizing through-vias and embedded conductive lines in vertical and subsurface dimensions, the patent routes power and signals beneath the active circuit surface. This frees up valuable top-side IC real estate for additional functional circuitry while maintaining complete circuit functionality.
Solution Approach 2:
The embedded conductive lines and through-via structures serve multiple functions: they provide power delivery, signal routing, and electrostatic discharge (ESD) protection pathways. This multi-functionality reduces the need for separate dedicated structures, thereby conserving IC real estate.
3Object-affected harmful factors
If ESD protection structures are added for protection, then electrostatic discharge protection is achieved, but IC real estate consumption increases prohibitively
Solution Approach 1:
The embedded conductive lines and through-via network is designed to serve dual purposes: normal power/signal routing and ESD protection. During ESD events, these existing structures provide low-impedance discharge pathways without requiring additional dedicated ESD protection circuitry, thereby avoiding prohibitively large real estate consumption.
Data Source
AI summary
A method can include receiving a first and a second power supply voltage at terminals disposed at a first side of an IC device. Rows of insulated gate field effect transistors (IGFETs) can be provided as a second side of the IC device. Each IGFET can include first and second source/drains (S/Ds), multiple channels, and a control gate that surrounds the channels. Coupling the first or second power supply voltage from one of the terminals to a first S/D of an IGFET via conductive vias and conductive lines. The conductive vias connected to adjacent conductive lines can be offset from one another in the first direction. Corresponding devices and systems are also disclosed.