Integrated Circuit Well Scanning for Localized SEL Detection
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Solution Overview
Problem
Conventional circuits for detecting single event latch-up (SEL) in integrated circuits (ICs) are complex, require multiple signature vectors, fail to identify the root cause of bit flipping, and cannot accurately locate the SEL within the device, leading to increased complexity and power overhead.
Innovation Solution
An integrated circuit (IC) with a detection circuit that includes a selection circuit, comparison circuit, and fault collection and control management circuit, which uses a scanning multiplexer and counter to periodically scan wells, compare input signals with a threshold signal, and generate a fault signal to locate and address SEL, reducing the need for multiple signature vectors and overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional circuits use multiple signature vectors to detect SEL, then detection capability is improved, but device complexity and power overhead increase
Solution Approach 1:
The detection circuit is segmented into three functional modules: selection circuit (with scanning multiplexer and counter), comparison circuit (with comparator and reference voltage generator), and fault collection and control management circuit. Each module performs a specific function, allowing the complex detection task to be divided into manageable parts that reduce overall circuit complexity while maintaining detection capability.
Solution Approach 2:
The scanning multiplexer serves multiple functions: it selects input signals from multiple wells, enables periodic scanning of all wells, and works with the counter to generate select signals. This multi-functionality reduces the need for separate dedicated circuits for each well, thereby reducing device complexity while maintaining comprehensive SEL detection capability.
2Measurement precision
If conventional circuits use multiple signature vectors for SEL detection, then detection accuracy is improved, but power consumption increases
Solution Approach 1:
The detection circuit performs periodic scanning of wells using a counter that generates periodic select signals for the scanning multiplexer. Instead of continuously monitoring all wells simultaneously, the circuit periodically scans through each well in sequence. This periodic action maintains detection accuracy while significantly reducing power consumption compared to continuous simultaneous monitoring of all wells.
Solution Approach 2:
The reference voltage generator extracts only the essential threshold reference signal needed for comparison, rather than using multiple complex signature vectors. By extracting only the critical comparison reference, the circuit achieves sufficient detection accuracy with minimal power overhead, eliminating the need for multiple power-intensive signature vector generation circuits.
3Measurement precision
If conventional circuits scan all wells continuously, then SEL location accuracy is improved, but device complexity increases
Solution Approach 1:
The counter acts as an intermediary between the clock signal and the scanning multiplexer, generating the select signals that control which well is being scanned. This intermediary component simplifies the control logic by providing a systematic way to generate sequential select signals, reducing the complexity of coordinating multiple well scans while maintaining accurate SEL location capability.
Solution Approach 2:
The scanning multiplexer and counter are pre-configured to systematically scan through all wells in a predetermined sequence. This preliminary arrangement of scanning order and control logic eliminates the need for complex real-time decision-making about which well to scan next, reducing circuit complexity while ensuring comprehensive and accurate SEL location detection.
Data Source
AI summary
An integrated circuit (IC) for detecting single event latch-ups (SELs) includes a plurality of wells of a memory circuit and a detection circuit. The detection circuit includes a selection circuit, a comparison circuit, and a fault collection and control management circuit. The selection circuit selects a well of the plurality of wells to sense a voltage or a current in the selected well. The well is selected based on a select signal that indicates a location of the well. The comparison circuit compares the sensed voltage or current with a predetermined threshold to generate a fault signal that may be indicative of the SEL in the selected well. The SEL may be indicative of a fault in the memory circuit. The fault collection and control management circuit determines corrective actions based on the detection of the location of the SEL.