Integrated CMOS MEMS Die Reducing PCB Footprint
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The use of separate CMOS and MEMS semiconductor chips on a printed circuit board consumes a significant amount of surface area, and existing methods to integrate them, such as mounting MEMS on top of CMOS chips, are not feasible for all CMOS chip sizes.
Innovation Solution
Forming CMOS MEMS support circuits and MEMS devices on the same semiconductor wafer in adjacent regions, allowing for selective connection during the wire bonding step to create integrated dice, which reduces the printed circuit board footprint by packaging both on the same die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate CMOS and MEMS semiconductor chips are used on a printed circuit board, then functional integration is achieved, but printed circuit board surface area increases significantly
Solution Approach 1:
The patent merges CMOS circuits and MEMS devices into a single integrated semiconductor chip by forming both types of structures on the same semiconductor wafer. The wafer is divided into first regions containing CMOS structures and second regions containing MEMS structures, which are then processed together to create a unified device that combines both functional elements on one chip, eliminating the need for separate chips and reducing PCB area.
Solution Approach 2:
The semiconductor wafer serves multiple functions by simultaneously hosting both CMOS circuits and MEMS devices during fabrication. The same wafer substrate and processing infrastructure are used to create diverse functional elements (CMOS logic and MEMS sensors/actators), making the fabrication system universal and enabling integrated multi-functional chips that reduce overall system footprint.
2Area of stationary object
If MEMS semiconductor chip is mounted on top of CMOS semiconductor chip, then footprint is reduced, but this approach is not feasible for all CMOS chip sizes
Solution Approach 1:
Instead of mounting one chip on another, the patent merges CMOS and MEMS structures at the wafer level before dicing. Both types of structures are formed on the same semiconductor wafer in adjacent regions, and the wafer is then diced to produce individual integrated chips that contain both CMOS and MEMS elements, making the solution applicable to all chip sizes without mechanical mounting constraints.
Solution Approach 2:
The patent transitions from a vertical stacking approach (mounting MEMS on top of CMOS) to a lateral integration approach where CMOS and MEMS structures are formed side-by-side on the same wafer plane. This dimensional shift from vertical to lateral arrangement enables integration for all chip sizes by utilizing the wafer surface area efficiently during fabrication, then separating them through dicing.
3Ease of manufacture
If the same fabrication steps are performed to form identical structures, then manufacturing consistency is maintained, but device diversity (CMOS and MEMS) cannot be achieved on the same wafer
Solution Approach 1:
The patent applies local quality by dividing the semiconductor wafer into different regions with distinct structures: first regions contain CMOS structures formed with CMOS fabrication steps, while second regions contain MEMS structures formed with MEMS fabrication steps. Each region receives localized processing appropriate to its device type, allowing both CMOS and MEMS devices to be manufactured on the same wafer with consistent quality control while maintaining device-specific characteristics.
Solution Approach 2:
The semiconductor wafer is segmented into multiple regions, each dedicated to a specific device type (CMOS or MEMS). This segmentation allows different fabrication processes to be applied to different segments of the same wafer, enabling the production of diverse device types while maintaining manufacturing consistency within each segment. The segmented approach facilitates selective processing and subsequent dicing to produce integrated chips.
Data Source
AI summary
Various semiconductor devices can be formed at the end of a common fabrication process, thereby significantly improving manufacturing flexibility, by selectively wiring bonding different CMOS circuits to different MEMS, which are formed on the same semiconductor die. A semiconductor device that has a number of CMOS circuits and a number of MEMS is formed on the same semiconductor wafer in adjacent regions on the wafer, and then diced such that the CMOS circuits and the MEMS are formed on the same die. After dicing, different CMOS circuits and different MEMS can be selectively connected during the wire bonding step to form the different semiconductor devices.