Integrated Common Source Power MOSFET Reducing Parasitic Capacitance
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Solution Overview
Problem
Existing power MOSFET devices face challenges in integrating independent drain and gate terminals in a single package, leading to high parasitic capacitance and losses, especially in high-frequency and high-current applications like LLC resonant converters, due to the conventional structure where the bottom surface corresponds to ground, requiring multiple silicon dice and causing mechanical and cost issues.
Innovation Solution
The development of an integrated common-source power MOSFET device with a substrate, epitaxial layer, sinker region, body region, source region, and gate region, where the sinker region extends through the epitaxial layer and substrate, and a trench filled with metal material, allowing for a single die integration with a common source terminal on the back, reducing parasitic capacitance and inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple MOSFETs are integrated in a single package with conventional structure, then independence of drain and gate terminals is achieved, but gate-drain parasitic capacitance increases and conduction losses increase
Solution Approach 1:
The source terminal is moved from the front surface to the back surface of the semiconductor substrate, utilizing the third dimension (depth) to reposition electrical contacts. This spatial rearrangement reduces the physical distance between source and drain regions while minimizing parasitic capacitance between gate and drain, thereby reducing conduction losses in high-frequency applications
2Adaptability or versatility
If multiple silicon dice are used to achieve independent terminals, then terminal independence is achieved, but device complexity and manufacturing cost increase
Solution Approach 1:
Multiple MOSFET devices are integrated into a single silicon die by sharing common source regions and substrate connections. The back-surface source terminal allows multiple devices to be electrically connected to a common source potential while maintaining independent gate and drain control, eliminating the need for multiple separate silicon dice and reducing assembly complexity
3Ease of manufacture
If conventional MOSFET structure with bottom surface ground is used, then manufacturing simplicity is maintained, but parasitic capacitance and inductance increase
Solution Approach 1:
The conventional MOSFET structure is inverted by moving the source terminal from the front surface (where it would be close to the gate) to the back surface of the substrate. This inversion of the traditional layout reduces the loop area for current flow and minimizes parasitic inductance, while also reducing gate-drain capacitance, thereby lowering energy losses in high-frequency switching applications
Data Source
AI summary
An integrated power MOSFET device formed by a substrate); an epitaxial layer of N type; a sinker region of P type, extending through the epitaxial layer from the top surface and in electrical contact with the substrate; a body region, of P type, extending within the sinker region from the top surface; a source region, of N type, extending within the body region from the top surface, the source region delimiting a channel region; a gate region; a source contact, electrically connected to the body region and to the source region; a drain contact, electrically connected to the epitaxial layer; and a source metallization region, extending over the rear surface and electrically connected to the substrate and to the sinker region.