Integrated Cooling Assembly With Nested Coolant Chamber for Chip Heat

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Solution Overview

Problem

Existing cooling systems for high-power density chips face inefficiencies due to design and manufacturing limitations, leading to increased operating temperatures that degrade performance and reliability, and contribute to unsustainable energy consumption in large-scale computing.

Innovation Solution

Integrated cooling assemblies with enhanced coolant chamber volumes and increased surface area, utilizing direct bonding of substrates with native or thermal oxide layers to facilitate efficient thermal transfer from semiconductor devices to coolant fluids.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If conventional cooling systems are used with standard heat dissipation devices, then the system structure is simple and easy to manufacture, but cooling efficiency is reduced due to insufficient surface area for thermal transfer

Engineering Contradiction:
Improvecooling efficiencyVSAvoidcooling system structure
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The cold plate is integrated directly into the device package substrate, with the coolant chamber nested within the substrate structure. The sidewalls of the coolant chamber extend downwardly to define a volume that is part of the substrate itself, creating a nested configuration that maximizes cooling surface area without adding external cooling components.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The coolant chamber width is designed to be greater than the device width, extending the cooling surface area in the lateral dimension. This dimensional expansion allows the coolant to contact a larger surface area of the device, improving thermal transfer efficiency without increasing the vertical profile of the cooling system.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Power

If chip performance is improved through increased gate density and multi-core microprocessors, then computing power increases, but thermal flux increases leading to elevated chip temperatures that degrade performance and reliability

Engineering Contradiction:
Improvecomputing powerVSAvoidchip temperature
Core Design Contradiction:
PowerVSTemperature

Solution Approach 1:

A dielectric material is provided between the device and the cold plate, serving as an intermediary that facilitates thermal transfer while maintaining electrical isolation. This dielectric layer enables efficient heat conduction from the high-power device to the coolant without creating electrical short circuits.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If operating temperatures are reduced to maintain performance and reliability, then component lifespan is extended, but energy consumption for cooling increases

Engineering Contradiction:
Improvecomponent lifespanVSAvoidcooling energy consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The integrated cold plate system uses the device package substrate itself to form the coolant chamber, eliminating the need for separate external cooling systems. The coolant chamber is self-contained within the substrate structure, allowing efficient heat removal without requiring additional energy-intensive cooling infrastructure.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Improves cooling efficiency by effectively transferring heat from semiconductor devices to coolant fluids, reducing operating temperatures and extending the lifespan of electronic components while minimizing energy consumption.

Implementation Method 1

cold plates with surfaces that facilitate more efficient thermal transfer of heat from a semiconductor device to coolant fluid

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

preparing first and second substrates for bonding using a plasma activation process

Methodology Applied
Scientific EffectPlasma: Plasma

Data Source

PatentUS20250336686A1Integrated cooling assemblies for advanced device packaging and methods of manufacturing the same
Publication Date: 2025.10.30 ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC
  • US20250336686A1 patent drawing
  • US20250336686A1 patent drawing
  • US20250336686A1 patent drawing

AI summary

A method of manufacturing a device package. The method comprises patterning a first substrate to form patterned regions comprising a thermal oxide layer. The method further comprises directly bonding the patterned regions of the first substrate to a second substrate to form a bonding interface. The bonded first and second substrates form an integrated cooling assembly comprising a coolant chamber volume. Portions of the first substrate exposed to the coolant chamber volume comprise a native oxide layer.