Integrated Data Driver Reducing Bezel Area

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Solution Overview

Problem

The increasing demand for thinner and lighter electronic devices with improved visual effects poses challenges in reducing the bezel area, which limits the space for hardware elements and circuit wirings, making it difficult to design efficient display devices.

Innovation Solution

A data driver comprising a boost circuit, gate clock generation circuit, level shift circuit, and data drive circuit, integrated with a display device that includes a power supply circuit, timing controller, and gate driver, allowing for reduced printed circuit board elements and wiring space, enabling smaller bezels and simplified circuit design.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If the display range is increased, then the visual effect is improved, but the area occupied by the bezel is reduced

Engineering Contradiction:
Improvedisplay rangeVSAvoidbezel area
Core Design Contradiction:
Area of moving objectVSArea of stationary object

Solution Approach 1:

The patent merges the timing controller and data driver into a single integrated device. The timing controller generates timing signals that are directly used by the data driver without requiring external synchronization signals, eliminating the need for additional synchronization wiring in the bezel area. This integration reduces the bezel area while maintaining the display range.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The integrated device performs multiple functions: it generates timing signals, processes display data, and drives the display panel all within a single unit. The timing controller and data driver share common functional resources, allowing the system to maintain full functionality with reduced hardware footprint and smaller bezel area.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Area of moving object

If the display range is increased, then the visual effect is improved, but the area for configuring hardware elements and circuit wirings is reduced

Engineering Contradiction:
Improvedisplay rangeVSAvoidhardware configuration area
Core Design Contradiction:
Area of moving objectVSArea of stationary object

Solution Approach 1:

The patent combines the timing controller and data driver into one integrated device, reducing the number of separate hardware elements that need to be configured. This merger decreases the area required for hardware configuration and simplifies the circuit wiring, as the integrated device internally manages timing signal distribution without requiring extensive external wiring.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If multiple data drivers are used to drive the display, then the pixel driving capability is improved, but additional synchronization signals are required

Engineering Contradiction:
Improvepixel driving capabilityVSAvoidsynchronization signal requirement
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The integrated timing controller and data driver device can drive multiple display panels simultaneously using a single device. The timing controller generates timing signals that are distributed internally to multiple data driver outputs, enabling multi-panel driving without requiring additional synchronization signals between separate data drivers, thus maintaining high pixel driving capability while reducing system complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10192515B2Display device and data driver
Publication Date: 2019.01.29 AU OPTRONICS CORP
  • US10192515B2 patent drawing
  • US10192515B2 patent drawing
  • US10192515B2 patent drawing

AI summary

A data driver for a display device comprises a first boost circuit, a first gate clock generation circuit, a first level shift circuit, and a data drive circuit. The first boost circuit is used to receive a supply voltage value and generate at least one preset voltage value. The first gate clock generation circuit is electrically coupled to the first boost circuit, and is used to receive a plurality of timing signals and at least one preset voltage value, and generate at least one first timing signal. The first level shift circuit is used to receive the at least one first timing signal and generate at least one gate timing signal. The data drive circuit is used to receive the timing signals, and generate a plurality of display data signals.